PCI debugging device, method and system

Details PCI debugging device, method and system PCI debugging device, method and system

1999-12-13

2003-02-25

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S044000

Reexamination Certificate

active

06526525

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88114691, filed Aug. 27, 1999.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a computer system debugging device and method. More particularly, the present invention relates to a debugging device, method and system for a computer system having a peripheral component interconnection (PCI) bus.
2. Description of Related Art
FIG. 1
is a block diagram showing a PCI bus system connecting various components of a conventional computer system. As shown in
FIG. 1
, a central processing unit
10
is coupled to the PCI bus
14
via a host bridge
12
. The host bridge
12
is further coupled to a system memory
11
. The master controller of several PCI compatible peripheral devices such as a graphic adapter
16
a
, an expansion bus bridge
16
b
, a LAN adapter
16
c
and a SCSI host bus adapter
16
d
can also be coupled to the PCI bus
14
. Each of these master controllers is able to send out a request (RST) signal demanding the use of the PCI bus
14
. The host bridge
12
serves as an arbitrator that sends out grant (GNT) signals to the controller when the PCI bus
14
is available.
Data transmission between PCI compatible devices (such as the master controllers or the north bridge of a computer chipset) are controlled by a few interface control signals. A cycle frame (FRAME) is issued from an initiator (can be the master controller or the north bridge) indicating the initialization of a data access operation and the duration therein. As soon as the FRAME signal is out, data transaction via the PCI bus begins. A low potential for the FRAME signal indicates data transmission is in progress. After the initiation of data transaction, the address bus AD will send out a valid address during the address cycle. In the meantime, the command/byte enable (CBE[
3
:
0
]) signal lines will send out a valid bus command (according to PCI specification) so that the target device knows the data transaction mode demanded by the initiator. In general, the four bits of the command/byte enable signal lines are capable of coding up to a maximum of 16 different commands, and each command is defined in detail in the PCI specification. After the effective address is out, a data cycle begins in which data is transmitted through the address bus AD. In the meantime, byte enable signals are sent so that data can be transmitted. When the transmission of FRAME signal stops, the last set of data is transmitted and no more in the current transaction. An initiator ready (IRDY) signal and a target ready (TRDY) signal are also used by the system for displaying the readiness of the initiating device and the target device in data transaction. In a data read operation, the IRDY signal indicates that the initiator is ready to receive the demanded data. In a data write operation, the TRDY signal indicates that the target device is ready to receive the demanded data. A stop (STOP) signal is used by the target device to request a termination of data transaction from the initiator.
FIG. 2
is a timing diagram showing the various signals in the PCI bus interface during a read operation. The period within which data are transmitted via the PCI bus is known as a bus transaction cycle
20
. The bus transaction cycle
20
includes an address cycle
22
and several data cycles, for example,
24
a
,
24
b
and
24
c
. Each data cycle
24
a/b/c
can be further divided into a wait cycle
26
a/b/c
and a data transfer cycle
28
a/b/c
. The following is a brief description of the PCI bus interface during a read operation for illustrating the control signals according to PCI specification.
During cycle T
1
, a FRAME signal is sent by the initiator indicating the start of a data transaction while a start address is put on the address bus AD lines to locate the target device of the transaction. In the meantime, a read command is transmitted through the CBE lines. After the delivery of the read command, a byte enable signal is put on the CBE lines. The byte enable signals are sent throughout the data cycles (including
24
a
,
24
b
and
24
c
). During cycle T
2
, the initiator submits an initiator ready signal IRDY indicating its readiness for data transmission. However, the target device is still not ready yet. Hence, the target device keeps preparing the data while the initiator idles in the wait cycle
26
a
of the data cycle
24
a
. During cycle T
3
, the target device has prepared all the necessary data for transmission, thereby sending out a target ready TRDY signal. Therefore, in data cycle
28
a
, both IRDY and TRDY are out and so the initiator can begin to read data from the target device. During cycle T
4
, the target device no longer issues the target ready TRDY signal, which signals the end of the first set of transmission data. Meanwhile, a set of data is prepared inside the target device. Again, the initiator enters a wait cycle
26
b
within the data cycle
24
b
. During cycle T
5
, the target ready TRDY signal is issued indicating the second set of data is ready. The second set of data is ready by the initiator in cycle
28
b
when both the IRDY and the TRDY signals are issued. When the initiator has insufficient time to read all the data from the target device as in cycle T
6
, the IRDY signal terminates. Since the TRDY signal is still out, the wait cycle
26
c
is activated by the initiator. As soon as the initiator is ready again as in cycle T
7
, the IRDY signal is re-issued. The initiator reads the data from the target device during data transfer cycle
28
c
when both IRDY and TRDY signals are issued, thereby completing a single read operation.
For the engineers engaged in PC hardware maintenance and development as well as researchers and students experimenting with PCs, the ISA bus card should be quite familiar. The ISA bus card is an indispensable tool for system debugging, repair and signal display. Compared with a logic analyzer, the ISA bus is a rather inexpensive and useful analytical tool. However, due to the continual increase in operating frequency in most PC system (for example, over 133 MHz for CPU, over 66 MHz for AGP and over 33 MHz for PCI bus), the ISA bus operating at mere 8 to 10 MHz has fallen too much behind other devices in speed. Consequently, the ISA bus is likely to be completely replaced by PCI bus in the near future. In fact, most manufacturers of main computer board have stopped adding an ISA bus slot on the main board.
However, only very simple PCI display cards having no termination capability are available in the PC market. These display cards is only capable of displaying address, data and command signals. In addition, each display card must rely on the I/O CHANNEL READY signal of an ISA bus debug card for halting the system temporarily. Therefore, given that a main computer board no longer has an ISA bus slot, debugging and repair can hardly proceed. Hence, there is an urgent demand for a PCI debugging device having some halting capability.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a PCI debugging device with a PCI interface. The user of the PCI debugging device is capable of halting the system and retrieving system information such as the address, data and command signals once the device is plugged into the PCI interface slot of the system. In addition, an ISA bus debug card is unnecessary.
A second object of the invention is to provide a method for debugging a system with a PCI interface such that system operation can be halted and address, data and command signals of the system can be displayed.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a PCI debugging device with a PCI interface. The PCI interface includes a request signal, a grant signal and a target ready signal. The system includes a debugging mode. If the request signal is enable while the system is in the debugg

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