PCI-compliant interrupt steering architecture

Details PCI-compliant interrupt steering architecture PCI-compliant interrupt steering architecture

1998-08-11

2001-02-20

Lefkowitz, Sumati (Department: 2781)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S048000

Reexamination Certificate

active

06192439

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to computer systems. More particularly, the invention relates to an interrupt steering device for use in a PCI-compliant computer system.
BACKGROUND OF THE INVENTION
Interrupts are a commonly used mechanism that peripheral devices use to request the service of a central processing unit (CPU). For example, a parallel port connected to a printer can generate an interrupt to the CPU requesting that the CPU transmit additional characters to the printer. In this way, the CPU is able to perform other tasks until the printer requires service.
FIG. 1A
illustrates an exemplary interrupt-driven computer system
100
. There is shown a host CPU
102
and a bus bridge
104
connected to a host bus
106
. The bus bridge
104
contains an interrupt routing mechanism
108
and an interrupt controller
110
. The bus bridge
104
is connected to a Peripheral Component Interface (PCI) bus
112
and an Industry Standard Architecture (ISA) bus
114
. One or more peripheral devices
116
A-
116
N are connected to the PCI bus
112
(herein referred to as PCI devices) and one or more peripheral devices
118
A-
118
M are connected to the ISA bus
114
(herein referred to as ISA devices).
The interrupt routing mechanism
108
receives the interrupts from the PCI devices
116
and routes them to an appropriate interrupt request (IRQ) signal. The interrupts from the ISA devices
118
are IRQ signals which are transmitted directly to the interrupt controller
110
. The IRQ signals are received by the interrupt controller
110
which generates an appropriate interrupt to the host CPU
102
.
Each PCI device
116
can be an add-in board or a component embedded on the board containing the PCI bus
112
. Four interrupt pins are associated with each PCI device
116
and are herein referred to as pin A, pin B, pin C, and pin D. Pin A is typically associated with the INTA# interrupt signal, pin B is associated with the INTB# interrupt signal, pin C is associated with the INTC# interrupt signal and pin D is associated with the INTD# interrupt signal. Single-function PCI devices utilize pin A and multi-function PCI devices can utilize more than one interrupt pin. The interrupt pins associated with each PCI device
116
can be connected to the system board traces in a variety of ways. An example of one such way is shown in FIG.
1
B.
There is shown three PCI devices,
116
A,
116
B,
116
C, where the interrupt traces or signals are shared between the three PCI devices,
116
A-
116
C. An interrupt signal is shared between the PCI devices
116
in order to compensate for the limitation of four interrupts. Interrupt trace or signal INTA# is tied to interrupt pin B of PCI device
1
116
A, interrupt pin C of PCI device
2
116
B, and interrupt pin A of PCI device
3
116
C. Interrupt signal INTB# is tied to interrupt pin C of PCI device
1
116
A, interrupt pin A of PCI device
2
116
B, and interrupt pin B of PCI device
3
116
C. Likewise, interrupt signal INTC# is tied to interrupt pin A of PCI device
1
116
A, interrupt pin B of PCI device
2
116
B, and interrupt pin C of PCI device
3
116
C. All of the D pins are tied to the INTD# signal.
Each of the interrupt signals, INTA#-INTD#, is hardwired to a separate input of the interrupt routing mechanism
108
. The interrupt routing mechanism
108
is used to assign each interrupt signal, INTA#-INTD#, to a specific interrupt request signal, IRQ
1
-IRQ
L
. The interrupt controller
110
receives the interrupt request signals, IRQ
1
-IRQ
L
, and in response asserts a corresponding interrupt request to the host CPU
102
.
A recent trend in the computing industry has been to use intelligent peripheral devices to control portions of the I/O activity ongoing in a computer system. In this way, the CPU is relieved of controlling these tasks and can be utilized to perform other tasks. An example of such an intelligent device is a redundant array of inexpensive disks (RAID) controller which is shown in FIG.
2
.
There is shown an exemplary computer system
130
utilizing a RAID controller
132
to control the transfer of data to and from external storage devices
134
A-
134
B. The RAID controller
132
is connected to a PCI bus
112
. Additional PCI devices
116
A-
116
N can be connected to the PCI bus
112
as well. In addition, a bus bridge
104
connects the PCI bus
206
to a host bus
212
, to which is coupled to a host CPU
102
. The bus bridge
104
includes an interrupt routing mechanism
108
that receives interrupts from each of the PCI devices and the RAID controller
132
and which generates a corresponding IRQ signal that is transmitted to an interrupt controller
110
. The interrupt controller
110
, in turn, generates a corresponding interrupt to the host CPU
102
.
The RAID controller
132
includes a processor module
138
that is in communication with the PCI bus
112
and an internal bus
136
. One or more small computer system interface (SCSI) controllers
140
A-
140
N or the like can be connected to the internal bus
136
. The processor module
138
can include a processor, an interrupt router, and an interrupt controller (all not shown) that receive and service the interrupts generated from the devices connected to the internal bus
136
.
A drawback with this computer system
130
is that the host CPU
102
receives the interrupts from each of the peripheral devices
132
,
116
connected to the PCI bus
112
. This unnecessarily burdens the host CPU
102
thereby degrading the overall performance of the computer system
130
. In order to improve the performance of the computer system
130
, it would be beneficial for the RAID controller
132
, or other intelligent peripheral device, to control the interrupts generated from the other PCI devices
116
rather than the host CPU
102
. In this way, the CPU
102
is not burdened with servicing these interrupts and is able to proceed with processing other tasks.
SUMMARY OF THE INVENTION
The present invention pertains to an interrupt steering mechanism that enables interrupt signals to be steered to intelligent devices other than a host CPU. In particular, the interrupt steering mechanism can be used to steer interrupt signals generated from peripheral devices to an Intelligent I/O (I2O) device which processes the interrupt signals, thereby relieving the host CPU from processing these interrupt signals.
The interrupt steering mechanism includes an interrupt steering device and an interrupt assist device. An interrupt steering mechanism is associated with each device that receives the interrupts and controls which interrupts are received by the device. In particular, the I2O controller is associated with a first interrupt steering mechanism and the host CPU is in communication with a second interrupt steering mechanism. The first interrupt steering mechanism is used to steer interrupts to the I2O controller and the second interrupt steering mechanism is used to steer interrupts to the host CPU.
The interrupt assist device enables the interrupt steering devices to route the interrupt signals in the desired manner, which can be to the host CPU, to the intelligent peripheral device, or to any combination thereof. The interrupt assist devices can be a programmable mechanism that is set by the user through configuration software and the system BIOS.
The interrupt steering and assist devices enable the intelligent peripheral device to handle and process interrupts from other devices. In this way, the host CPU is relieved of processing these interrupts and is free to process other tasks thereby improving the overall performance of the computer system. Furthermore, the interrupt steering mechanism utilizes the signals from the PCI bus and does not require any sideband or additional signals apart from the PCI bus. In this way, the interrupt steering mechanism is compliant with the PCI bus protocol.


REFERENCES:
patent: 3812463 (1974-05-01), Lahti et al.
patent: 4604500 (1986-08-01), Brown et al.
patent: 4769768 (1988-09-

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