Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-04-17
2001-08-28
Etienne, Ario (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S110000, C710S240000, C710S052000, C710S036000
Reexamination Certificate
active
06282598
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a PCI bus system wherein an initiator and a target are connected via a PCI (Peripheral Component Interconnect) bus.
Generally, a PCI bus system of this type has been formed wherein a central processing unit (CPU) is connected to a PCI bus via a host—PCI bridge (arbiter), and a PCI device is connected to the PCI bus. In such a PCI bus system, an expansion bus bridge is often connected to the PCI bus while an expansion device is connected to this expansion bus bridge via an expansion bus.
In this PCI bus system, data transfer is carried out via a host between connecting the CPU and the host—PCI bridge in synchronism with a 66 MHz clock, for example. On the other hand, data transfer is also carried out via the PCI device or the PCI bus provided between the PCI device and the expansion bus bridge in synchronism with a 33 MHz clock. If the expansion bus is formed by an ISA bus, then data is transferred on the expansion bus in synchronism an 8 MHz clock.
In a system constructed in this way, the data transfer speed on the host bus is about 8 times the data transfer speed on the expansion bus, whilst the data transfer speed on the PCI bus is about 4 times the data transfer speed on the expansion bus. In PCI bus system of this kind, the access operations from the initiator to the target include access operations from the CPU to the PCI device or expansion bus device, and access operations from the PCI device to the expansion bus device. Due to the difference in respective operating speeds, the transfer performance in these access operations is limited by the lower speed device. Each device forming a target is also required to wait for a long period of time until the data for transmission to the initiator is prepared. For example, if the explanation bus device is used as a target, supposing that it takes only three clock counts from an access request until initial data transmission in the expansion bus device, this clock count will represent a long time period of 24 clocks at the host bus. Therefore, before data transmission, the host bus will be in a state of occupation by the target for a long period of time.
It often takes time (latency) from reception of a data read-out request from the initiator until the start of data output, and even if this period of time is long, the bus will be in a state of occupation by the target.
A PCI bus system has been proposed, which involves delayed transactions, whereby, if the bus remains in an occupied state for no purpose, a retry request, is output from the target to the initiator and the bus is provisionally released. In this system, when making access from the initiator to the target, the initiator transmits an address to the target when it is granted right of use of the PCI bus by the arbiter. If the target is temporarily in a state whereby it cannot respond to this access, a response signal is output to the initiator, and a retry request seeking a suspension of data transfer is also transmitted to the initiator.
In this case, having received the retry request, the initiator executes the same access operation again with respect to the target after a prescribed period of time has elapsed. When the access operation is reimplemented, the target will not necessarily have assumed a state which allows it to transfer data, and therefore it is possible that even when the access operation is reimplemented, the target will again issue a retry request to the initiator. Consequently, when delayed transactions are used, since an initiator receiving a retry request does not know the timing at which the transaction request is to be resubmitted, a process of request and retry request is repeated between the initiator and target.
In any case, a composition of this kind entails drawbacks in that the PCI bus is often in an occupied state for no purpose and only a slow transfer performance can be achieved.
It is an object of the present invention to provide a PCI bus system whereby the efficiency of use of the PCI bus is raised and transfer performance from target to initiator can be improved.
It is a further object of the present invention to provide a PCI bus system which employs delayed transactions whereby the efficiency of use of the PCI bus can be improved.
It is yet a further object of the present invention to provide a target which is capable of retaining and transmitting the time period from access to data transfer, namely, latency information.
SUMMARY OF THE INVENTION
According to a mode for implementing the present invention, in a PCI bus system comprising an initiator and a target, which transmits data to the initiator by means of access from the initiator, a PCI bus system is obtained wherein the target comprises means for storing latency information indicating the time period required until the data is transmitted after receiving access from an initiator, and the latency information is transmitted to the initiator when access from the initiator is received.
According to a further mode for implementing the present invention, a target is obtained which is capable of storing the time period required until data is transmitted after receiving access from an initiator, as latency information, and transmitting this information to an initiator in response to an access operation.
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Etienne Ario
NEC Corporation
Ostrolenk Faber Gerb & Soffen, LLP
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