PCI bus switch architecture

Details PCI bus switch architecture PCI bus switch architecture

2000-09-22

2004-03-30

Auve, Glenn A. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S310000

Reexamination Certificate

active

06715023

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to computer buses. More particularly, this invention relates to a PCI (Peripheral Component Interconnect) bus switch architecture.
Typical computer systems have multiple interconnected PCI buses that transfer “traffic” (e.g., is data and control information) among various logic devices (e.g., a microprocessor, video adapter, and other peripherals) and between those logic devices and, for example, a system controller or central processing unit. Because a PCI bus has a limited load capacity, PCI-to-PCI bridges are used to increase the number of PCI devices that can be coupled in a system. In such systems, a system controller is coupled to a main or first level PCI bus (i.e., PCI Bus
0
). Each group of logic devices is typically coupled to a local PCI bus, which is coupled to a PCI bridge. The PCI bridge is also coupled to the main PCI bus. If the number of devices required is very large, multiple PCI bridges are coupled to the main bus.
Traffic transfers between, for example, an initiator logic device A, coupled to a local bus
1
, and a target logic device B, coupled to a local bus
2
, can execute in many ways depending on the capabilities of the PCI bridge. A basic sequence is as follows: logic device A requests and obtains access to local bus
1
; a PCI bridge
1
coupled to local bus
1
then requests and obtains access to main bus
0
; a PCI bridge
2
coupled to main bus
0
then requests and obtains access to local bus
2
; and lastly, traffic is transferred from logic device A to logic device B.
A disadvantage of such a bus architecture is high traffic latency. This refers to the time required to transfer traffic. More often than not, delays are incurred while waiting for bus access. Furthermore, each PCI bridge typically includes a primary port coupled to the main bus, a secondary port coupled to a local bus, and a port controller coupled between the primary and secondary ports. Thus, a traffic transfer between any two logic devices not coupled to the same local bus incurs notable time delays through the two PCI bridges (i.e., four PCI interfaces). Such time delays undesirably slow overall system performance.
Another disadvantage of such traffic transfers is low throughput. Throughput can be measured in megabytes per second and refers to the data transfer rate through a system. Traffic transfers generally can only be executed between the two PCI bridges on the same bus. Other traffic transfers between non-locally coupled logic devices normally have to wait until the current transfer completes before access to the main bus can be obtained. Referring to the above traffic transfer example between logic devices A and B, a traffic transfer between logic devices C and D, for example, as well as other traffic transfers to device B, have to wait until the A to B transfer is complete. Conceivably, many traffic transfers can be waiting at any given moment, adversely affecting throughput. Thus, traffic throughput is generally limited by the PCI bridge operating at the slowest speed (typically measured in megahertz) and having the narrowest bus width (e.g., 32 bits).
In view of the foregoing, it would be desirable to provide a bus switch architecture that has low traffic latency.
It would also be desirable to provide a bus switch architecture that has high traffic throughput.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a bus switch architecture that has low traffic latency.
It is also an object of this invention to provide a bus switch architecture that has high traffic throughput.
In accordance with this invention, a bus switch architecture is provided that has low latency and high throughput. This is accomplished by providing a PCI bus switch having a primary port controller that interfaces with, for example, a system controller, and a plurality of secondary port controllers that each interface with one or more logic devices. The primary and secondary port controllers couple to a crossbar switch. Each port controller can advantageously operate at speeds independent of the other port controllers. Thus, for example, the primary port controller can advantageously transfer traffic at higher speeds than the secondary port controllers. Moreover, the PCI bus switch can transfer traffic from non-overlapping pairs of logic devices substantially simultaneously, thus improving throughput. Such transfers between logic devices not coupled to the same local bus no longer need to be processed through two primary ports and routed across the main bus, but instead are processed through secondary port controllers and the crossbar switch. These transfers are not dependent on the availability of the main bus. Moreover, latency of such device-to-device transfers is lowered by eliminating traffic transfers through two PCI interfaces (i.e., the primary ports of two PCI bridges).


REFERENCES:
patent: 5345228 (1994-09-01), Franaszek et al.
patent: 5701413 (1997-12-01), Zulian et al.
patent: 6138185 (2000-10-01), Nelson et al.
patent: 6189058 (2001-02-01), Jones et al.
patent: 6327253 (2001-12-01), Frink
patent: 6381664 (2002-04-01), Nishtala et al.

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