PCI bus cycle single-step interruption debug card

Details PCI bus cycle single-step interruption debug card PCI bus cycle single-step interruption debug card

2005-07-05

2005-07-05

Iqbal, Nadeem (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C710S015000

Reexamination Certificate

active

06915458

ABSTRACT:
The single-step debug card using the PCI interface according to the present invention utilizes a bus master to send out an REQ# signal to request issuing a control during the PCI bus cycle to be inspected. The address, data, command, and byte enable (BE#) of the bus cycle are locked and displayed through LEDs for single-step debugging. Through a switch circuit, a TRDY# ready signal is sent out. A device selection signal (DEVSEL#) is raised to HIGH at the same time the TRDY# ready signal finishes so as to notify the bus master on the single-step interruption debug card to end the cycle for single-step debugging.

REFERENCES:
patent: 5838899 (1998-11-01), Leavitt et al.
patent: 6032271 (2000-02-01), Goodrum et al.
patent: 6123735 (2000-09-01), Raghavan et al.
patent: 6751754 (2004-06-01), Tsai et al.

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