PCI bus bridge with transaction forwarding controller for avoidi

Details PCI bus bridge with transaction forwarding controller for avoidi PCI bus bridge with transaction forwarding controller for avoidi

1998-09-28

2000-11-07

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 8, 710 52, 710100, 710101, 710107, 710108, 710110, 710113, 710128, 710129, 710130, 713400, 713401, 714 2, 714 44, 714 56, 714 57, G06F 1238, G06F 1240

Patent

active

061450448

ABSTRACT:
A bus bridge which can prevent invalid data from being transferred from a secondary PCI bus to a primary PCI bus even when an SCSI controller or another device provided with a memory the content of which is cleared after a read, is connected to the secondary PCI bus. In a controller, a transaction is processed as a delayed transaction. A combination circuit generates a switching logic signal in accordance with a command or an address included in the transaction. In accordance with the memory content, a bus release controller restricts transmission by a transaction forward controller of a control signal for stopping the transaction issued on the primary PCI bus. Instead of restricting the transmission of the control signal, the time-out period of the buffer memory may be prolonged.

REFERENCES:
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patent: 5768602 (1998-06-01), Dhuey
patent: 5864653 (1999-01-01), Tavallaei et al.
patent: 5878238 (1999-03-01), Gan et al.
patent: 5887194 (1999-03-01), Carson et al.
patent: 5983306 (1999-11-01), Corrigan et al.
"PCI Local bus Specification",Revision 2.1, 3.3.3.3. -3. 4 pp.49-55.
"PCI to PCI Bridge Architecture Specification", Revision 1.0, April 5, 1994, pp. 1-55.

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