PCI bridge having latency inducing serial bus

Details PCI bridge having latency inducing serial bus PCI bridge having latency inducing serial bus

1999-05-14

2003-06-17

Lefkowitz, Sumati (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S300000, C710S310000

Reexamination Certificate

active

06581125

ABSTRACT:

TECHNICAL FIELD
This invention relates to interfaces between bus systems of computer devices, and more particularly, to PCI bridge configurations having memory portions provided at physically separate locations coupled together via a bus.
BACKGROUND OF THE INVENTION
The transfer of information within a computer system is handled by one or more buses. A typical computer system includes a number of devices, or agents, such as microprocessors, display devices, storage devices and input/output devices. One or more system buses are used to interconnect these agents in order to transfer control, address and data signals. More recently, computer systems have employed multiple buses, with individual agents being couple to one of the buses.
Multiple-bus computer systems utilize bus bridges in order to connect together the buses such that agents on one bus can couple to agents on another bus. Accordingly, bus bridges provide an interface between two bus systems which enable the connection between subsystems of a computer system. One example involves coupling together a processor and an expansion bus of a computer system via a bus bridge.
One type of bus that has recently become popular is the peripheral component interconnect (PCI) local bus. The PCI bus was designed to place agents, or peripheral components, in closer electrical proximity with a central processing unit so as to improve system performance for graphics, network and multimedia applications.
FIG. 1
illustrates a prior art computer system
30
having a conventional PCI bus bridge
10
coupled between a primary PCI bus
12
and a secondary PCI bus
14
. According to one implementation, primary PCI bus
12
is a processor bus and secondary PCI bus is an I/O bus. However, it is understood that bus bridge
10
can be used to couple together any two buses
12
and
14
, not merely a processor bus and an I/O bus.
PCI bus bridge
10
includes a primary PCI interface
16
, a secondary PCI interface
18
, configuration registers
20
and first-in-first-out (FIFO) queues
22
and
24
. An agent
26
is coupled to primary PCI bus
12
and another agent
28
is coupled to secondary PCI bus
14
. In use, configuration registers
20
operate as a temporary storage buffer for storing data that is being transferred between FIFO queues
22
and
24
. FIFO queue
22
is used to store requests that are issued on primary PCI bus
12
and target an agent
26
on bus
12
. Similarly, FIFO queue
24
is used to store requests that are issued on secondary PCI bus
14
and target an agent
28
on bus
14
. As shown in
FIG. 1
, the status of FIFO queues
22
and
24
are available to both primary PCI interface
16
and secondary PCI interface
18
at all times.
In operation, the configuration registers
20
are written and read by primary PCI bus
12
. Registers
20
control the behavior of primary PCI interface
16
, secondary PCI interface
18
and FIFO queues
22
and
24
. However, the primary PCI bus
12
and secondary PCI bus
14
cannot be physically -separated apart since the configuration registers
20
are loaded via primary PCI bus
12
, and serve to control the action of both primary PCI bus
12
and secondary PCI bus
14
. Such inability to separate PCI bus bridge
10
between two buses
12
and
14
reduces the number of available applications. For example, such PCI bus bridge
10
cannot be used to couple a notebook computer having a PCI bus with a docking station having a second PCI bus.
As another example, such PCI bus bridge
10
cannot be used to place a primary PCI bus (and main processor) within the upper screen display housing of a laptop computer, while placing the secondary PCI bus (and associated components) in the lower housing of a laptop computer. Such implementation would be desirable in order to separate the heat-generating main processor from secondary operating components which reduces heat build-up within the lower housing. However, such implementation would require the PCI bus bridge to operate through a flex cable that is fed through a hinge formed between the upper and lower housings. The prior art PCI bus bridge
10
is not capable of realizing such desired configuration.
Therefore, there exists a need to provide for a PCI bus bridge that enables physical separation between a primary PCI bus and a secondary PCI bus. Furthermore, there exists a need to provide for a PCI bus bridge that enables decoupling of physically separate components of a PCI bus bridge. Yet even furthermore, there exists a need to provide a memory configuration that accommodates a latency inducing serial bus.
SUMMARY OF THE INVENTION
An apparatus and a method are provided for configuring a PCI bus bridge between two physically separate locations via two portions, or halves, of a PCI bus bridge. The PCI bus bridge includes a serial bus that is used to connect together the two portions of the bus bridge. The bus bridge joins together two PCI busses that are capable of being separated both electrically and physically. A pair of FIFO queues are provided at each end of the serial bus to allow transfers in each direction. According to one construction, the PCI bus bridge has a connector that allows the two portions of the bridge to be removably coupled together. The serial bus of the bus bridge provides a latency inducing bus that is used to connect together the two halves of the PCI bus bridge, which introduces latency when transmitting information from one memory portion of the bus to another memory portion of the bus. Two sets of redundant configuration registers are also provided, one set in the primary side of the bridge and another set in the secondary side of the bridge. The serial bus of the bus bridge provides a serial communication link that continuously transmits required FIFO status bits across the serial communication link. According to one specific implementation, two separate locations are provided on a laptop and a docking station. According to another specific implementation, two separate locations are provided within the upper and lower housings of a laptop computer.
According to one aspect of the invention, a computer system includes a host processor, a first PCI bus, a second PCI bus and a bus bridge. The first PCI bus is coupled with the host processor. The bus bridge interconnects the first and second PCI buses. The bus bridge includes a first portion having a first bridge memory, a second portion having a second bridge memory, and a latency inducing serial bus interconnecting the first portion and the second portion.
According to another aspect of the invention, a bridge is provided that is coupled between a first bus and a second bus. The bridge includes a first bridge portion, a second bridge portion, and a serial bus. The first bridge portion has a first bridge memory. The second bridge portion has a second bridge memory. The serial bus couples together the first bridge portion and the second bridge portion.
According to even another aspect of the invention, a computer system includes a notebook computer, a docking station, and a bus bridge. The notebook computer has a first PCI bus. The docking station has a second PCI bus. The bus bridge is coupled between the first PCI bus and the second PCI bus. The bus bridge includes a first bridge memory, a second bridge memory, and a serial bus. The serial bus is provided between the first bridge memory and the second bridge memory.
According to yet another aspect of the invention, a method is provided for mating a first PCI bus with a second PCI bus. The first PCI bus is provided by a first agent and the second PCI bus is provided by a second agent. The method includes the steps of: providing a bus bridge having a first portion with a first bridge memory and a second portion with a second bridge memory; wherein the first portion and the second portion are connected for communication by a serial bus; transmitting data between the first portion and the second portion; when a receiving portion of one of the first bridge memory and the second bridge memory approaches an overflow li

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