Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-11-12
2001-06-12
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000
Reexamination Certificate
active
06247086
ABSTRACT:
BACKGROUND OF THE INVENTION
PCI stands for “peripheral component interface” defined by the PCI Special Interest Group in an effort to stem development of various local bus architectures. The PCI bus may be connected to adapters requiring fast inter-adapter access and/or system memories with accesses near to the host processor native bus speed. Read and write transfers over the PCI bus are burst transfers with any negotiated length defined by the initiating and target device. The prior art is familiar with PCI bus architectures.
The prior art is also familiar with PCI bridge chips that connect together two PCI buses. These bridge chips can be used, for example, in transferring data from an initiating PCI bus to a target PCI bus. One prior art bridge chip is the DEC21154 chip from Intel, for example. Such prior art bridge chips generally provide for sequential transfer of large bursts of data across the bridge; though they cannot effectively handle multiple delayed requests and completions without regard to the order in which they were received or completed.
Some prior art PCI bridges do not provide for delayed transactions, which are instead handled sequentially. Other prior art PCI bridges implement delayed transactions, but place ordering restrictions on either the requests or the completions. These bridges thus either implement a single delayed transaction, or multiple delayed transactions which require completion in a specific order relative to being received on the initiating bus and completion on the target bus.
The prior art bridge chips present a problem, for example, in SCSI RAID controller systems—known in the art—where the primary data path is not across the bridge. SCSI (Small Computer System Interface) defines a bus interface that is typically used between a host computer and associated data storage devices, such as the RAID (Redundant Array of Inexpensive or Independent Disks). In dual PCI bus SCSI RAID controller systems, the bridge is used to transfer small command blocks between the central processing unit (“CPU”) of the host computer and the other devices in the system. A single large burst provided by prior art PCI bridges offers little performance advantage to SCSI RAID controller systems.
SCSI RAID controller systems would thus benefit from a PCI bridge chip which processes multiple command blocks simultaneously; and one object of the invention is thus to provide such a PCI bridge chip.
Another object of the invention is to provide a PCI bridge chip that sacrifices large data bursts in favor of multiple, small bursts, that are typical of command traffic seen in a SCSI RAID system.
Yet another object of the invention is to provide a PCI bridge chip that handles multiple SCSI requests efficiently and in parallel, instead of sequentially as in the prior art. Still another object of the invention is to provide an improved RAID controller with increased bandwidth and I/O's (inputs and outputs) per second.
These and other objects will become apparent in the description that follows.
SUMMARY OF THE INVENTION
In one aspect, the invention provides a PCI bridge chip for communicating command data between a primary PCI bus and a secondary PCI bus. A primary command transaction logic manages command data transfers from the primary PCI bus to the secondary PCI bus. The primary delayed transaction logic has a plurality of primary buffers for buffering command transactions to be issued on the secondary PCI bus selectively. A secondary command transaction logic manages command data transfers from the secondary PCI bus to the primary PCI bus. The second delayed transaction logic has a plurality of secondary buffers for buffering command transactions to be issued on the primary PCI bus selectively.
In another aspect, the primary command transaction logic can include three primary buffers, each with a memory length of 128 bytes, for example.
In a similar aspect, the secondary command transaction logic can include three secondary buffers, each with a memory length of 128 bytes, for example.
In still another aspect, the primary command transaction logic includes a primary PCI interface, that interfaces with the primary PCI bus, and a secondary PCI interface that interfaces with the secondary PCI bus. A primary to secondary delayed transaction logic manages command data through the primary buffers, in this aspect.
The primary command transaction logic can further include a primary buffer management and completion compare logic to match an incoming request with completed transactions in the primary buffers. The primary command transaction logic completes a PCI transaction when a match is found, storing the incoming request in one of the primary buffers, if available, and issues a retry on the primary PCI bus when a match is not found. The primary command transaction logic issues a retry on the primary PCI bus when a match is not found and when none of the primary buffers are available.
In yet another aspect, the primary command transaction logic includes primary transaction arbitration and ordering logic to route command data transactions within the primary buffers.
In still another aspect, the primary command transaction logic includes one or more primary write buffers to store posted writes that are not delayed transactions. At the appropriate time, the posted writes compete for access to the secondary bus and the primary transaction arbitration and ordering logic routes posted writes onto the secondary PCI bus.
In another aspect, the secondary command transaction logic includes a “secondary PCI interface, to interface with the secondary PCI bus, and a primary PCI” interface to interface with the primary PCI bus. A secondary to primary delayed transaction logic manages command data through the secondary buffers, in this aspect.
The secondary command transaction logic can further include secondary buffer management and completion compare logic to match an incoming request with completed transactions in the secondary buffers. The secondary command transaction logic completes a PCI transaction when a match is found, stores the incoming request in one of the secondary buffers, if available, and issues a retry on the secondary PCI bus when a match is not found. The secondary command transaction logic issues a retry on the secondary PCI bus when a match is not found and when none of the secondary buffers are available.
In another aspect, the secondary command transaction logic includes secondary transaction arbitration and ordering logic to route command data transactions within the secondary buffers. The secondary command transaction logic can for example include one or more secondary write buffers to store posted writes that are not delayed transactions. At the appropriate time, the posted writes compete for access on the primary bus and the secondary transaction arbitration and ordering logic routes posted writes onto the primary PCI bus.
A bridge chip of the invention can further include a memory controller section for coupling non-command data to memory connected to the bridge chip. By way of example, the memory can be RAM or SDRAM; and the non-command data can include large burst data. This memory can alternatively be made integrally within the bridge chip.
In another aspect, a method is provided for communicating command data between a primary PCI bus and a secondary PCI bus, including the steps of: routing command data from the primary PCI bus to the secondary PCI bus through a plurality of primary buffers; buffering, within the primary buffers, command transactions to be issued on the secondary PCI bus; routing command data transfers from the secondary PCI bus to the primary PCI bus through a plurality of secondary buffers; and buffering, within the secondary buffers, command transactions to be issued on the primary PCI bus.
In other aspects, the invention includes the step of routing large data bursts from the primary PCI bus into memory, and/or routing large data bursts from the secondary PCI bus into the memory.
The invention is next described further in connection
Adaptec, Inc.
Beausoleil Robert
Chung-Traus X.
Patton & Boggs LLP
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