Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-11-14
2004-11-23
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S022000, C714S011000
Reexamination Certificate
active
06823475
ABSTRACT:
This invention relates to computer systems, and is concerned especially with computer systems of the kind that involve the interconnection or clustering of a multiplicity of processors.
BACKGROUND OF THE INVENTION
It is known to form a computing system of the above-specified kind by interconnecting the processing units of a multiplicity of personal computers (PCs) and operating them in parallel with one another; such systems are sometimes referred to as ‘Beowulf clusters’. The central processing units (CPUs) of PCs provide significant computing power at relatively-low cost, and advantage has been taken of this to form systems of the above-specified kind having very high computing power comparable with that of a specially-designated supercomputer, at a fraction of the supercomputer-cost. In such systems a multiplicity of PC-CPUs are interconnected and operated in parallel with one another as separate nodes of a local area network. These systems using clustered CPUs require the development of special software to enable parallel operation, and are generally slower than their supercomputer counterparts, but have significant advantage economically.
The CPUs of PCs are not designed to have the extended reliability to be expected of a supercomputer, so computing systems of the known form involving clustered CPUs are, in comparison, susceptible to faults. A fault occurring in an individual CPU will disrupt processing of the current application, and although the application can in general be re-started without replacement of the faulty unit, the disruption and loss of computing time involved is undesirable.
It is one of the objects of the present invention to provided a computer system of the said above-specified kind, which whilst having the potential for cost advantage of the known clustered PC-CPU systems, in less susceptible to fault disruption.
SUMMARY OF THE INVENTION
According to one aspect of the present invention there is provided a computer system of the said above-specified kind wherein power supply to each processor is from a common power-supply means having fault-tolerating redundancy.
The computer system of the present invention may, especially for cost-advantage, utilize processors that are of a form such as used in the context of PC computers. However in accordance with the present invention, rather than powering each processor from its own power-supply unit as in the case of the known form of computer system referred to above utilising PC-CPUs, they are powered from common power-supply means. The power-supply units of PC-CPUs especially, are not designed to have long fault-free operation so the likelihood of a fault arising in any of a multiplicity of clustered PC-CPUs, can be significantly high. The individual power-supply units might be replaced by units with a higher standard of reliability, but it is generally more economical to provide a common power-supply means and invest this with an even higher standard of reliability and, moreover, to include fault-toleration redundancy within it.
The processors of the computer system according to the invention may be carried by individual printed-circuit boards, for example PC motherboards, that are mounted together side-by-side within a rack-mounting. The rack-mounting may be contained within a cabinet together with the power-supply means.
The power-supply means may involve one or more power-supply units each of which comprises a plurality of power-supply modules which operate in parallel with one another in supplying power to the processors. The modules may each include diode or other circuitry that is responsive to the occurrence of a fault within the module (eg reduction in its voltage output in relation to that of the other module) to isolate that module effectively from the processors. Where more than one power-supply unit is involved, they may act in parallel with one another to power all the processors together.
REFERENCES:
patent: 5450285 (1995-09-01), Schlemmer
patent: 5577205 (1996-11-01), Hwang et al.
patent: 5598041 (1997-01-01), Willis
patent: 5659789 (1997-08-01), Hausauer et al.
patent: 5664089 (1997-09-01), Byers et al.
patent: 5745670 (1998-04-01), Linde
patent: 5784641 (1998-07-01), Sueyoshi et al.
patent: 5848230 (1998-12-01), Walker
patent: 5909583 (1999-06-01), Hayes et al.
patent: 6181549 (2001-01-01), Mills et al.
patent: 6189107 (2001-02-01), Kim et al.
patent: 6191499 (2001-02-01), Severson et al.
patent: 6195754 (2001-02-01), Jardine et al.
patent: 6201319 (2001-03-01), Simonelli et al.
patent: 6263452 (2001-07-01), Jewett et al.
patent: 6289467 (2001-09-01), Lewis et al.
patent: 6295571 (2001-09-01), Scardamalia et al.
patent: 6345369 (2002-02-01), Kitamorn et al.
patent: 6392872 (2002-05-01), Doustou et al.
patent: 6449729 (2002-09-01), Sanders et al.
patent: 6542997 (2003-04-01), Rolls et al.
patent: 6597073 (2003-07-01), Check
patent: 2295057 (1996-05-01), None
Baderman Scott
Damiano Anne L.
LandOfFree
PC-CPU motherboards with common fault-tolerant power supply does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with PC-CPU motherboards with common fault-tolerant power supply, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PC-CPU motherboards with common fault-tolerant power supply will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3360925