PC core logic chipset comprising a serial register access bus

Details PC core logic chipset comprising a serial register access bus PC core logic chipset comprising a serial register access bus

1997-09-11

2000-02-29

Thai, Xuan M.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 2, 710 22, 710 28, 710100, 710126, 710260, 710266, 712 38, 713502, G06F 1300, G06F 1342

Patent

active

060322136

ABSTRACT:
A computer system includes first and second integrated circuits. The first integrated circuit provides a first input/output bus operating in accordance with a first protocol, such as ISA. The first input/output bus includes a plurality of address and data lines respectively providing address and data information. The second integrated circuit includes a plurality of second functional blocks at least some of which interface to legacy devices. The first integrated circuit includes a host controller circuit, coupled to the first input/output bus and for coupling to a register access bus which includes a register data out and a register data in signal line. The register access bus connects the first and second integrated circuits. The host controller circuit receives address and data information from the input/output bus and serially provides the address and data information to the data out line. A target controller circuit on the second integrated circuit is coupled to the register access bus. The target controller circuit receives the serially provided address and data information and provides the address and data information, over a second representation of the input/output bus, the second representation being at least a subset of the first protocol and including a plurality of internal address lines and a plurality of internal data lines coupled to the second functional blocks. Write operations take place to memory locations in the second integrated circuit from a write operation begun on the first integrated circuit and read operations take place from memory locations in the second integrated circuit for read operations begun on the first integrated circuit.

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