Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-11-23
2002-01-15
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S363000, C370S506000, C370S907000
Reexamination Certificate
active
06339628
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
In a transmission system, such as SDH (Synchronous Digital Hierarchy) or SONET (Synchronous Optical Network), in which each data frame consists of an overhead area and a payload area and is capable of accommodating a payload starting at any point within the payload area by including a pointer in a designated location in the overhead area to indicate the starting point of the payload accommodated in the payload area, the present invention relates to an apparatus for requesting a pointer action in a data frame at the transmitting side of a transmission apparatus in case the clock at the transmitting side goes out of synchronization with the clock at the receiving side, and also relates to the transmission apparatus containing such an apparatus.
In this specification, a description will be given by taking a system in which VC-
4
is inserted as a payload in STM-n defined in ITU-T recommendations G.707, G.708, G.709, as an example of the transmission system that allows a payload to be inserted starting at any point within the payload area by using a pointer, but it will be appreciated that the present invention is not limited to this particular example, but can be applied to every kind of transmission system such as first described.
2. Description of the Related Art
To accommodate a VC-
4
in an STM-n, first a pointer is appended to form a signal called AU-
4
. Appending a section overhead (SOH) to the AU-
4
signal results in the formation of an STM-
1
signal; the STM-n signal is a signal formed by byte-interleaving n STM-
1
signals. When creating the AU-
4
from the VC-
4
, the frame of the VC-
4
signal can start at any point with respect to the beginning of the frame of the AU-
4
signal and the position of the VC-
4
can be changed at intermediate points along the transmission path. The pointer indicates where the VC-
4
signal begins with respect to the starting point of the AU-
4
signal.
A transmission apparatus for receiving and transmitting an STM-n signal needs to perform a pointer adjustment operation to adjust frequency and phase differences by increasing or decreasing the pointer value and thus changing the relative position of the VC-
4
within the STM-n frame so that the VC-
4
can be transmitted correctly without dropping or duplication, when the received STM-n frame is not synchronous with the transmitted STM-n frame, or if the frames go out of synchronization for some reason when they are normally synchronous.
In the pointer adjustment operation, when the phase of the received frame is advanced by more than a predetermined amount with respect to the phase of the transmitted frame, a negative justification is performed in which three bytes in the VC-
4
are inserted in a designated location in the overhead area and the pointer in the next frame is decremented by one. To indicate the negative justification, the D bits (bits
8
,
10
,
12
,
14
, and
16
in the pointer word) of the immediately preceding pointer are inverted. Conversely, when the phase of the received frame is delayed by more than a predetermined amount with respect to the phase of the transmitted frame, a positive justification is performed in which three positive justification bytes are inserted in a designated location in the payload area and the pointer in the next frame is incremented by one. To indicate the positive justification, the I bits (bits
7
,
9
,
11
,
13
, and
15
in the pointer word) of the immediately preceding pointer are inverted. If there is a constant frequency difference between the received and transmitted frames, a pointer action of positive or negative justification should take place periodically.
In the prior art, this pointer adjustment operation has been performed in the following manner. The pointer contained in the received frame is examined in order to locate the range of the VC-
4
in the received frame, and a clock is generated by selectively inhibiting portions of the AU-
4
clock (or STM-
1
clock) other than the portions thereof corresponding to the VC-
4
. At the transmitting end also, a similar clock is generated by selectively inhibiting portions of the clock other than the portions thereof corresponding to the VC-
4
. These clocks are also used to write and read the VC-
4
data in and out of a buffer memory. After frequency dividing these partially inhibited clock signals by respective frequency dividers having a prescribed dividing factor (for example, 17), their phases are compared, and when the phase difference exceeds a predetermined threshold, a pointer action request for positive justification or negative justification in the transmitted frame is issued.
In the STM-
1
, the overhead area to be inhibited appears in a clustered manner with the 9-byte overhead appearing alternately with the 261-byte payload, which is also the case with other frame formats of this kind, so that clock inhibiting is performed in a clustered fashion. Accordingly, during the period when one of the clocks is being inhibited in a clustered fashion, the phase comparison cannot be made correctly and justification requests occur at unevenly spaced intervals, as will be described in detail later. This leads to the problem that when the original signal carried in the VC-
4
is finally reproduced, low-frequency jitter, which is difficult to eliminate, will appear.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a pointer action requesting apparatus capable of issuing pointer action requests at evenly spaced intervals of time, and a transmission apparatus containing such an apparatus.
According to the present invention, there is provided an apparatus for effecting a request to change a payload relative position in an outgoing transmission frame in order to enable a payload contained in an incoming data frame to be mapped properly into an outgoing data frame in a transmission performed using a data frame containing an overhead area and a payload area and capable of accommodating a payload in any part of the payload area, comprising: an incoming-side PLL circuit for accepting at an input thereof a clock synchronized to data within the incoming data frame and containing selectively inhibited portions that are equal in number to portions of the data frame other than the portion of the payload contained therein, and for rearranging the timings of the clock at substantially equally spaced intervals; an outgoing-side PLL circuit for accepting at an input thereof a clock synchronized to data within the outgoing data frame and containing selectively inhibited portions that are equal in number to portions of the data frame other than the portion of the payload contained therein, and for rearranging the timings of the clock at substantially equally spaced intervals; and a phase comparator circuit for performing a phase comparison between an output of the incoming-side PLL circuit and an output of the outgoing-side PLL circuit, and for outputting the result of the phase comparison as a relative position change request in the outgoing data frame.
According to the present invention, there is also provided an apparatus for effecting a request to change a payload relative position in an outgoing transmission frame in order to enable a payload contained in an incoming data frame to be mapped properly into an outgoing data frame in a transmission performed using a data frame containing an overhead area and a payload area and capable of accommodating a payload in any part of the payload area, comprising: an incoming-side inhibit signal generating circuit for outputting temporally dispersed inhibit signals equal in number to portions of the incoming data frame other than the portion of the payload contained therein; an incoming-side inhibit circuit for selectively inhibiting a clock synchronized to data within the incoming data frame, in accordance with the incoming-side inhibit signals, and for outputting the selectively inhibited clock; an outgoing-side inhibit signal generating circuit for outputting
Fujitsu Limited
Pham Chi
Phu Phuong
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