Patterning three dimensional structures

Details Patterning three dimensional structures Patterning three dimensional structures

2000-12-22

2003-09-30

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000

Reexamination Certificate

active

06627530

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to three-dimensional circuits and more particularly to the formation of three-dimensional circuits.
2. Background
Three-dimensional circuits are generally those in which active or passive circuit elements are formed over a surface of a planar substrate. A three-dimensional circuit typically interacts with circuit elements formed in a surface of a substrate. A typical monolithic integrated circuit has transistors and other structures formed at least in part in the substrate. A three-dimensional circuit may rely, for example, for signal operation or function on a substrate, but the operation of the circuit elements do not utilize a portion of the substrate. Implementation of three-dimensional circuit arrays include, but are not limited to, memory arrays, resistor arrays, and transistor arrays.
Commonly-owned, U.S. Pat. No. 6,034,882 titled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication” and co-pending U.S. patent application Ser. No. 09/560,626, titled “Three-Dimensional Memory Array Method of Fabrication,” describes, in one aspect, three-dimensional circuit arrays such as field programmable, nonvolatile memory arrays wherein circuits are fabricated in a vertical arrangement over rather than in a surface of a planar substrate, such as, for example, a semiconductor substrate.
In many instances, it is desirable from a processing standpoint to construct circuit arrays of multiple levels of similar materials. However, processing techniques such as cell definition through etch patterning often rely on materials of different composition to achieve desired patterning. Thus, what is needed are techniques for forming circuit arrays of similar material that offer consistent performance and distinguishable patterning avenues suitable for use in three dimensional circuit arrays.
SUMMARY OF THE INVENTION
The invention provides a technique for patterning circuit structures, including a technique wherein multiple layers of similar material may be selectively patterned to create desired structures.
In one embodiment, the method includes introducing a circuit structure over a substrate in a stacked configuration between a first level of signal line material and a second level of signal line material. The first and second levels of signal line material comprise similar material. The method also includes selectively patterning the second level of signal line material and at least part of the circuit structure, without patterning the first level of signal line material. In this manner, the invention provides a technique wherein multiple signal lines of similar material coupling a respective plurality of circuit levels may be incorporated and patterned sequentially without concern of disruption or damage to previously introduced and patterned signal lines.
One way the second signal line material is patterned exclusive of the first signal line material is by modifying the etch chemistry from a first chemistry that favors the etching of signal line material (e.g., second signal line material) to a second chemistry that disfavors the etching of signal line material prior to contacting, for example, the first signal line material.
A second way the second signal line material is patterned exclusive of the first signal line material is by including an etch stop between the first and second signal line material. Examples of suitable etch stop materials include, but are not limited to, materials that are transient or temporary in that, for example, the material may be removed or changed with subsequent processing (e.g., thermal processing). Alternatively, the etch stop material may form part of the three-dimensional circuit structure between the first and second signal line materials.
The invention also describes a technique for patterning a desired edge angle by modifying, for example, an etch chemistry between a first chemistry that is generally anisotropic and a second chemistry that has a horizontal component. According to this example, an edge angle that is slightly re-entrant (i.e., has a negative slope) may be realized.
Additional features, embodiments, and benefits will be evident in view of the figures and detailed description presented herein.


REFERENCES:
patent: 3576549 (1971-04-01), Hess et al.
patent: 3582908 (1971-06-01), Koo et al.
patent: 3634929 (1972-01-01), Yoshida et al.
patent: 3671948 (1972-06-01), Cassen et al.
patent: 3717852 (1973-02-01), Abbas et al.
patent: 3728695 (1973-04-01), Frohman-Bentchkowsky
patent: 3787822 (1974-01-01), Rioult
patent: 3863231 (1975-01-01), Taylor
patent: 3990098 (1976-11-01), Mastrangelo
patent: 4146902 (1979-03-01), Tanimoto et al.
patent: 4203123 (1980-05-01), Shanks
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
patent: 4281397 (1981-07-01), Neal et al.
patent: 4419741 (1983-12-01), Stewart et al.
patent: 4420766 (1983-12-01), Kasten
patent: 4442507 (1984-04-01), Roesner
patent: 4494135 (1985-01-01), Moussie
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4507757 (1985-03-01), McElroy
patent: 4543594 (1985-09-01), Mohsen et al.
patent: 4569121 (1986-02-01), Lim et al.
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 4820657 (1989-04-01), Hughes et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4876220 (1989-10-01), Mohsen et al.
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 4899205 (1990-02-01), Hamdy et al.
patent: 4922319 (1990-05-01), Fukushima
patent: 4943538 (1990-07-01), Mohsen et al.
patent: 5070383 (1991-12-01), Sinar et al.
patent: 5311039 (1994-05-01), Kimura et al.
patent: 5334880 (1994-08-01), Abadeer et al.
patent: 5391518 (1995-02-01), Bhushan
patent: 5441907 (1995-08-01), Sung et al.
patent: 5463244 (1995-10-01), De Araujo et al.
patent: 5536968 (1996-07-01), Crafts et al.
patent: 5675547 (1997-10-01), Koga
patent: 5737259 (1998-04-01), Chang
patent: 5792377 (1998-08-01), Belcher et al.
patent: 5835396 (1998-11-01), Zhang
patent: 6355567 (2002-03-01), Halle et al.
Drohman-Bentchkowsky, D., “A Fully Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory,” IEEE Journal of Solid-State Circuits, vol. SC-6, No. 5, Oct. 1971, pp. 301-306.
Sato, N., “A New Programmable Cell Utilizing Insulator Breakdown,” International Electron Devices Meeting, Washington, D.C., Dec. 1-4, 1985, pp. 639-642.
V. Subramanian, “Control of Nucleation and Grain Growth in Solid-Phase Cyrstallized Silicon for High-Performance Thin Film Transistors,” published 1998, pp. 1-140.

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