Patterning self-aligned transistors using back surface...

Details Patterning self-aligned transistors using back surface... Patterning self-aligned transistors using back surface...

2007-02-26

2009-12-08

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S157000, C257SE21410, C257SE21278, C257SE21253, C257SE21329, C257SE21347

Reexamination Certificate

active

07629206

ABSTRACT:
Fabrication methods for making thin film devices on transparent substrates are described. Gate, source, and drain electrodes of a transistor are formed on a transparent substrate. The widths of the drain electrode and source electrodes are greater than a width of the gate electrode. A dielectric layer is formed on the gate electrode. A semiconductor layer is deposited proximate to the gate, source and drain electrodes. Photoresist is deposited on the semiconductor. The photoresist is exposed to light directed through the transparent substrate so that the gate electrode masks the photoresist from the light. The semiconductor layer is removed in regions exposed to the light.

REFERENCES:
patent: 4689116 (1987-08-01), Coissard et al.
patent: 4834507 (1989-05-01), Kato et al.
patent: 4836650 (1989-06-01), Morin et al.
patent: 4918504 (1990-04-01), Kato et al.
patent: 5177577 (1993-01-01), Taniguchi et al.
patent: 5299041 (1994-03-01), Morin et al.
patent: 5339181 (1994-08-01), Kim et al.
patent: 5394258 (1995-02-01), Morin et al.
patent: 5402254 (1995-03-01), Sasano et al.
patent: 5441905 (1995-08-01), Wu
patent: 5610082 (1997-03-01), Oh
patent: 6184069 (2001-02-01), Wu
patent: 6543901 (2003-04-01), Moon
patent: 6563174 (2003-05-01), Kawasaki et al.
patent: 6927830 (2005-08-01), Chung et al.
patent: 7176488 (2007-02-01), Kim et al.
patent: 2002/0079501 (2002-06-01), Okada et al.
patent: 2006/0091793 (2006-05-01), Baude et al.
patent: 2006/0228974 (2006-10-01), Thelss
patent: 1662571 (2006-05-01), None
patent: 62106666 (1987-05-01), None
patent: 02245738 (1990-10-01), None
Ohya, “Thin Film Transistor of ZnO Fabricated by Chemical Solution Deposition”, Jpn. J. Appl. Phys., vol. 40, pp. 297-298, 2001.
Wagner, “Transparent Electronics”, Science, vol. 300, May 23, 2003.
J. Richard, M. Bonnel, B. Vinouze, J.L. Favennec, P. Weisse, U. Bessonnat, G. Gerard, S. Salaun, M. LeContellec, and F. Morin,Large LCD Panel Addressed by 320x320 TFT Array, Proceedings of the SID, vol. 26/3, 1985 , pp. 209-212.
Y. Lebosq, M. LeContellec, F. Morin, S. Salaun and P. Weisse,An Improved Design of Active Matrix LCD Requiring only Two Photolithrographic Steps, 1985 International Display Research Conference, CH2239 -2/85/0000-0034 © 1985 IEEE, pp. 34-36.
Arai, T. et al.,Nanostructure and electrical properties of anodized A1 gate insulator for thin film transistors, Mat. Res. Soc. Symp., vol. 424, p. 37 (1997).
R.A Street (ED.),Technology and Applications of Amorphous Silicon; ISBN 3-540-65714-2; Springer-Verlag Berlin Heidelberg 2000.
U.S. Appl. No. 11/678,865, filed Feb. 26, 2007, Haase et al.
U.S. Appl. No. 11/678,877, filed Feb. 26, 2007, Haase et al.

Affiliated with

Also associated with

Rating

Patterning self-aligned transistors using back surface... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Patterning self-aligned transistors using back surface..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Patterning self-aligned transistors using back surface... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4073102