Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-09-24
2003-11-25
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S159000, C438S160000, C438S200000, C257S059000, C257S061000, C257S066000, C257S072000
Reexamination Certificate
active
06653177
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a patterning method and a method of manufacturing a TFT (thin film transistor) matrix substrate and, more particularly, to a patterning method for connecting patterns to form a single pattern as a whole and a method of manufacturing a thin film transistor substrate utilizing the patterning method.
2. Description of the Related Art
TFT matrix type color liquid crystal displays have been spreading recently as displays of personal computers and wall-mount televisions. This has resulted in a trend toward liquid crystal displays with greater screens.
In order to manufacture such displays at low cost, it is important to form TFT matrices with less processing steps and higher yield, which is primarily achieved by photolithographic techniques utilizing reticles (exposure mask) capable of transferring a multiplicity of patterns simultaneously. Normally, one reticle (called one layer) is used for one patterning step.
In the case of a large screen which has a great substrate, it is difficult to transfer the entire pattern of one layer at a time for reasons associated with the structure of the exposure device. For this reason, the entire patterned region of one layer is divided into a plurality of sub-regions, and a plurality of reticles are provided to process each of the sub-regions. When the entire pattern is formed, each of the sub-regions of the same resist film is separately exposed by masking regions other than the sub-region to be exposed to form the entire pattern.
FIG. 4
schematically shows a TFT matrix substrate
50
. The number of pixels in
FIG. 4
is shown in a simplified manner. Basic pixel units
40
driven by TFTs
36
are arranged in the form of a matrix of 6 rows×9 columns. The configuration will now be briefly described. Gate bus lines
32
and drain bus lines
34
are arranged on a glass substrate
30
perpendicularly to each other, and TFTs
36
(the configuration of which will be described later) are provided near intersections between the gate bus lines
32
and drain bus lines
34
. The gates of the TFTs
36
are connected to the gate bus lines
32
, and the drains are connected to the drain bus lines
34
. Further, source electrodes of the TFTs
36
are connected to pixel electrodes
38
. A unit region formed by a TFT
36
, pixel electrode
38
, gate bus line
32
and drain bus line
34
connected each other is referred to as “basic” pixel unit', and a pattern in such a region is referred to as “basic unit pattern”.
When the TFT matrix as shown in
FIG. 4
is formed using two reticles, a method may be used in which the matrix is simply divided into two regions, i.e., the region of the first through fourth columns (left region) and the region of the fifth through ninth columns (right region) along a linear border line. As will be apparent from the plan view in FIG.
5
and the sectional view in
FIG. 6
(sectional view taken along the line A—A in FIG.
5
), a TFT
36
is formed such that a gate electrode
32
(a gate bus line
32
) overlaps a source electrode
36
S and a drain electrode
36
D in consideration to alignment accuracy and, as a result, a floating capacity Cgs is generated between the gate electrode
32
and source electrode
36
S. When the left and right regions described above are separately aligned to solve this, a difference may occur in the width of an overlap of the source electrode
36
S and gate electrode
32
between the TFTs
36
in the left region and the TFTs
36
in the right region. In this case, since the TFTs
36
in the left and right regions have different floating capacities Cgs, those regions will have different source electrode, which causes a difference in transmittance between them. As a result, a difference in luminance occurs between the two regions to cause unevenness of display. While the above example is divided in the lateral direction, division in the longitudinal direction may be adopted in addition to lateral division in practice because of a greater number of pixels, in which case misalignment can occur in all directions.
As a method of solving such unevenness of display, patterning methods are disclosed in Japanese Patent Laid-Open No. 236930/1997 and so on in which unit patterns of different exposure masks are mixed at a joint between groups of unit patterns formed by different exposure masks.
FIG. 7
is a schematic illustration of the conventional technique disclosed in the above-cited publication in which two (a pair of) reticles are shown. Reticles RTa
3
and RTb
3
are provided to form a TFT matrix of 6 rows×6 columns. Although there is exposure steps for a plurality of layers and different exposure patterns exist for respective layers in practice, for simplicity of description, simplified patterns of gate bus lines
66
, drain bus lines, TFTs
70
and pixel electrodes are shown here to clearly indicate basic pixel units
72
.
The TFT matrix having 6 columns is divided in two columns to define a first region (the first and second columns), a second region (the fifth and sixth columns) and a third region (the third and fourth columns), and the third region is a boundary portion to serve as a joint during pattern formation using the two reticles. Therefore, in the reticle RTa
3
, patterning regions
78
for exposing the basic pixel units
72
are provided in a region
100
corresponding to the first region, and patterning regions
78
and shading regions
76
which are non-patterning regions where no exposure occurs are provided in a staggered configuration in a region
300
a
′ corresponding to the third region. In the reticle RTb
3
, patterning regions
78
for exposing the basic pixel units
72
are provided in a region
200
corresponding to the second region, and patterning regions
78
and shading regions
76
which are non-patterning regions where no exposure occurs are provided in a staggered configuration that is the reverse of (complement to) that in the reticle RTa
3
in the region
300
a
′ corresponding to the third region. Therefore, the basic pixel units
72
in the third region are exposed and patterned when one of the reticles RTa
3
and RTb
3
is used and are not exposed when the other reticle is used because of the shading regions.
When such a boundary portion is provided to mix unit patterns associated with different exposure masks in the boundary portion, it is difficult to recognize a clear boundary even if any difference in luminance exits between the patterns formed using the different masks.
FIGS. 8 and 9
show parts of reticles used in a specific application of the patterning method shown in FIG.
7
. Reticles RTa
4
and RTb
4
are provided to form a TFT matrix pattern having nine columns as shown in
FIG. 4
in which the first and second columns are a first region; the eighth and ninth columns are a second region; and the third through seventh columns are a third region.
The reticle RTa
4
shown in
FIG. 8
is provided to pattern the first and third regions, and patterning regions
78
associated with basic pixel units
72
are provided in a portion corresponding to the first region (the first and second columns). In a portion corresponding to the third region (the third through seventh columns), there is provided patterning regions
78
associated with the regions of basic pixel units
72
and shading regions
76
similarly associated with the regions of basic pixel units
72
in a staggered configuration.
The reticle RTb
4
shown in
FIG. 9
is provided to pattern the second and third regions, and patterning regions
78
associated with basic pixel units
72
are provided in a portion corresponding to the third region (the eighth and ninth columns). In a portion corresponding to the second region (the third through seventh columns), there is provided patterning regions
78
associated with the regions of basic pixel units
72
and shading regions
76
similarly associated with the regions of basic pixel units
72
in a staggered configuration which is complementary to that
Fujitsu Display Technologies Corporation
Greer Burns & Crain Ltd.
Smith Matthew
Yevsikov Victor V
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