Patterning conductive metal layers and methods using same

Details Patterning conductive metal layers and methods using same Patterning conductive metal layers and methods using same

1998-09-03

2001-04-17

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S656000, C438S663000, C438S669000, C438S686000

Reexamination Certificate

active

06218297

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices and the fabrication thereof. More particularly, the present invention pertains to a method of patterning platinum and semiconductor devices including the same.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc., conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers of contact holes, vias, etc.
As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material.
Generally, various metals and metallic compounds, for example, metals such as ruthenium and platinum, have been proposed as the electrodes for at least one of the layers of an electrode stack for use with high dielectric constant materials. Many storage cell capacitors are fabricated which include electrode layers that are formed of a conductive material within a small high aspect ratio opening. One particularly preferred material for forming an electrode in a high dielectric capacitor is platinum. However, one of the problems typically associated with the use of platinum is the lack of a practical etch process. Thus, conventional techniques used to form a platinum electrode include CMP (chemical-mechanical polishing) or ion milling. However, these techniques pose particular problems when utilized for forming patterned platinum features. For example, CMP is typically used to achieve a planar surface over the entire wafer and/or chip. However, it may be difficult to polish a layer formed within a small high aspect ratio opening using CMP. Ion milling typically includes the use of a broad ion beam to impinge on the wafer surface in a defined direction with respect to the feature to be etched. However, due to the physical characteristics of platinum, ion milling is generally difficult to perform, for example, it is typically a relatively slow and non-selective process which may result in an over etching of underlying layers.
SUMMARY OF THE INVENTION
There is a need in the art to reliably and accurately pattern platinum, particularly when forming electrodes, e.g., as a lower or bottom electrode, in high dielectric capacitors. To overcome the problems described above, and others that will be readily apparent from the description below, a conductive layer is patterned utilizing an adhesion layer in accordance with the present invention. The patterned layer can be used in interconnection structures, e.g., contacts, vias, etc. Patterning the layer in accordance with the present invention likely results in a reduction of processing costs by eliminating some of the etching and/or CMP processing steps typically associated with formation of structures. A patterned layer formed in accordance with the present invention is preferably a conductive metal selected from the group consisting of platinum or ruthenium.
One aspect of the present invention provides a method for patterning a platinum layer in the fabrication of integrated circuits. The method includes providing a substrate assembly including a surface in a reaction chamber; forming a patterned metal-containing adhesion layer on the surface, resulting in at least one exposed surface region of the substrate assembly; forming platinum on the patterned metal-containing adhesion layer and the at least one exposed surface region of the substrate assembly; annealing the substrate assembly including the patterned metal-containing adhesion layer and the platinum thereon; and removing platinum from the at least one exposed surface region of the substrate assembly.
Another aspect of the present invention provides a method for forming a discontinuous conductive layer in the fabrication of integrated circuits. The method includes providing a substrate assembly in a reaction chamber, the substrate assembly having a surface including at least one metal-containing adhesion region separated by at least one surface region of the substrate assembly; forming a platinum layer on the surface of the substrate assembly; annealing the substrate assembly including the platinum layer thereon; and removing platinum from the at least one exposed surface region to form a discontinuous platinum layer on at least one metal-containing adhesion region.
Yet a further aspect of the present invention provides a method for forming a platinum layer in the fabrication of integrated circuits. The method includes providing a substrate assembly in a reaction chamber, the substrate assembly including a surface having a patterned metal-containing adhesion portion thereon; depositing a platinum layer on the surface of the substrate assembly and the patterned metal-containing adhesion portion thereon, wherein the platinum layer has a thickness of about 600 Å or less; annealing the substrate assembly at a temperature of about 1100° C. or less; and removing unadhered platinum from the surface of the substrate assembly such that a resulting patterned platinum layer has a configuration substantially that of the patterned adhesion portion.
Yet another aspect of the present invention provides a method for use in forming a capacitor. The method includes providing a substrate assembly, the substrate assembly including at least one surface; and forming an electrode on the at least one surface of the substrate assembly, wherein forming the electrode comprises at least forming a platinum electrode layer, wherein forming the platinum electrode layer includes: forming a metal-containing adhesion layer on the at least one surface, and forming the platinum layer only on the metal-containing adhesion layer. Preferably, forming the platinum electrode layer includes forming a layer of platinum on the at least one surface of the substrate assembly and the metal-containing adhesion layer; annealing the substrate assembly; and removing platinum on the at least one surface of the substrate assembly such that the platinum layer is formed only on the metal-containing adhesion layer.
Typically, the substrate assembly includes an opening defined therein, wherein the opening is defined by a bottom surface of the substrate assembly and at least one side wall extending therefrom and further wherein the metal-containing adhesion layer is formed on the surfaces defining the opening.
A further aspect of the present invention provides a method for forming a discontinuous conductive layer in the fabrication of integrated circuits. The method includes providing a substrate assembly in a reaction chamber, the substrate assembly having a surface including at least one metal-containing adhesion region separated by at least one surface region of the substrate assembly; forming a conductive metal layer on the surface of the substrate assembly, wherein the conductive metal layer comprises a metal different from a metal in the least one metal-containing adhesion region; annealing the substrate assembly including the conductive metal layer thereon; and removing conductive material metal from the at least one exposed surface region to form a discontinuous conductive metal layer on at least one metal-containing adhesion region. Preferably, the conductive metal layer comprises a metal selected from the group consisting of platinum or ruthenium.
Preferably, a conductive metal layer, e.g., platinum or ruthenium, has thickness of about 600 Å or less, and more preferably a thickness of

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