Patterned SOI regions in semiconductor chips

Details Patterned SOI regions in semiconductor chips Patterned SOI regions in semiconductor chips

1999-07-16

2001-12-25

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000, C257S329000, C257S330000, C257S350000, C257S904000, C257S349000

Reexamination Certificate

active

06333532

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to Silicon-On-Insulator (SOI) semiconductor chips and more particularly to patterned regions of SOI in bulk semiconductor material and further, to trenches formed at the perimeter of respective SOI regions to provide electrical isolation and to remove or control crystalline defects.
BACKGROUND OF THE INVENTION
It is well known that SOI based logic circuits show 20-30% higher performance than logic circuits comparably made on bulk-Si. Currently, Si wafers are ion implanted with oxygen such as 10
18
atoms/cm
2
to form a buried oxide region beneath the surface of the Si. The Si wafers are annealed to form a continuous buried oxide layer (BOX) beneath the surface that isolates electrically the top Si layer from the bulk Si below the BOX. The above process for making SOI wafers is known in the art as separation by implantation of oxygen (SIMOX). SOI wafers are then processed to form devices and/or circuits therein.
In the fabrication of CMOS circuits on bulk Si, shallow trench isolation (STI) has been used to provide electrical isolation between devices. A shallow trench is formed, filled with an insulator and then planarized by Chemical Mechanical Polishing (CMP).
In the fabrication of Dynamic Random Access Memories (DRAM), memory cells consisting of a field effect transistor and a capacitor have been used. IBM Corp. has developed the use of a deep trench capacitor for the memory cell such as described in U.S. Pat. No. 4,688,063 which issued Aug. 18, 1987 by Lu et al. entitled “Dynamic Ram Cell With MOS Trench Capacitor In CMOS.” A deep trench is formed and then the sidewalls and bottom are oxidized or coated with an insulator followed by filling the trench with a conductor such as doped poly silicon.
SUMMARY OF THE INVENTION
In accordance with the present invention, a structure for forming electrical devices therein and a method for making is described comprising a semiconductor substrate containing Si having an upper surface, and a plurality of spaced apart buried oxide regions formed by ion implantation of oxygen therein through openings in a patterned mask to provide a plurality of buried oxide regions under the surface of a single crystal silicon containing layer.
The invention further provides a method for forming a semiconductor layer over an insulator comprising the steps of forming a first mask on a substrate containing Si, implanting oxygen through the mask into the substrate and annealing the substrate to form a patterned buried oxide layer and a semiconductor layer there over.
The invention further provides a structure and method for forming bulk semiconductor regions and SOI regions on a wafer with trenches positioned at or near the perimeter of the SOI regions to provide electrical isolation and to control crystalline defect propagation and effects.
The invention further provides a structure and method for forming embedded DRAM and merged logic by forming Bulk Si regions with DRAM formed therein and SOI regions with merged logic (CMOS) formed therein.


REFERENCES:
patent: 4688063 (1987-08-01), Lu et al.
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 5864158 (1999-01-01), Liu et al.
patent: 5930643 (1999-07-01), Sadana et al.
patent: 10-107233 (1998-04-01), None
Understanding DRAM Operation, Applications note, IBM Corp. (1996).

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