Patterned-print thin-film transistors with top gate geometry

Details Patterned-print thin-film transistors with top gate geometry Patterned-print thin-film transistors with top gate geometry

2005-07-28

2008-03-18

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S159000, C438S160000, C257SE21412

Reexamination Certificate

active

07344928

ABSTRACT:
A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

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U.S. Appl. No. 11/184,304, Arias et al,. Patterned Structures Fabricated By Printing Mask Over Lift-Off Pattern, filed Jul. 18, 2005.

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