Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-10
2003-03-18
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000, C438S637000, C438S646000, C438S760000, C438S780000, C438S781000
Reexamination Certificate
active
06534396
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for passivating patterned conductor layers within microelectronic fabrications. More particularly, the present invention relates to methods for passivating, with dimensionally stabilized planarization, patterned conductor layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Integral to the fabrication of microelectronic fabrications is the fabrication within microelectronic fabrications of bond pads which are typically formed within a microelectronic fabrication as a terminal patterned conductor layer when fabricating the microelectronic fabrication. Bond pads are clearly desirable and essential within the art of microelectronic fabrication when fabricating microelectronic fabrications insofar as bond pads provide a means for electrically connecting and interconnecting various types of microelectronic fabrications to provide fully functional microelectronic fabrication products. Similarly, and also integral to the fabrication of microelectronic fabrications is the fabrication within microelectronic fabrications of passivation layers which generally passivate pond pads, but through which passivation layers are formed vias which access bond pads for purposes of electrically connecting and interconnecting various types of microelectronic fabrications when providing fully functional microelectronic fabrication products. Similarly, in turn, passivation layers are also clearly desirable and essential within the art of microelectronic fabrication insofar as passivation layers, in particular when having formed therethrough vias accessing bond pads, typically provide for edge passivation of bond pads which in turn provides for enhanced reliability of microelectronic fabrications within which are formed such edge passivated bond pads.
While both bond pads and passivation layers are thus clearly desirable in the art of microelectronic fabrication, both bond pads and passivation layers are not fabricated entirely without problems in the art of microelectronic fabrication. In that regard, it is often desirable within the art of microelectronic fabrication, but not always readily achievable within the art of microelectronic fabrication, to provide, with enhanced and dimensionally stabilized planarization, passivation layers passivating bond pads within microelectronic fabrications.
It is thus towards the foregoing object that the present invention is directed.
Various passivation methods and passivation materials have been disclosed in the art of microelectronic fabrication for forming passivation layers which passivate structures including but not limited to bond pads within microelectronic fabrications.
For example, Jin et al., in U.S. Pat. No. 5,883,001, discloses a passivation method and a passivation structure for passivating, with among other features, an enhanced optical clarity, an electrically erasable programmable read only memory (EEPROM) cell and an adjacent bond pad within a electrically erasable programmable read only memory (EEPROM) microelectronic fabrication. To realize the foregoing object, the passivation method and the passivation structure employ forming over the electrically erasable programmable read only memory (EEPROM) cell and the adjacent bond pad a sandwich composite planarizing dielectric layer construction comprising a pair of conformal silicon oxide dielectric layers between which is sandwiched a spin-on-glass (SOG) planarizing dielectric layer, and through which sandwich composite planarizing dielectric layer construction is formed a via accessing the bond pad while employing an isotropic etch method followed by an anisotropic etch method.
In addition, Dass et al., in U.S. Pat. No. 6,046,101, discloses a method for forming, with enhanced interfacial adhesion, a multi-layer passivation layer employed for passivating a bond pad within a microelectronic fabrication, wherein the multi-layer passivation layer comprises a silicon nitride passivation layer having formed thereover an otherwise generally minimally adherent polyimide passivation layer. To realize the foregoing object, the multi-layer passivation layer employs formed in-situ upon the silicon nitride passivation layer prior to forming thereover the otherwise generally minimally adherent polyimide passivation layer a silicon oxynitride adhesion promotion layer.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within microelectronic fabrications passivation layers which passivate bond pad layers within microelectronic fabrications, wherein the passivation layers are formed with enhanced and dimensionally stabilized planarization.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a passivation layer passivating a bond pad.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the passivation layer is formed with enhanced and dimensionally stabilized planarization.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a microelectronic fabrication. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is then formed over the substrate and passivating the topographic variation at the periphery of the patterned conductor layer a planarizing passivation layer formed of a thermally reflowable material. There is then formed upon the planarizing passivation layer a dimensionally stabilizing layer. Finally, there is then thermally annealed the microelectronic fabrication to form from the planarizing passivating layer a thermally annealed planarizing passivating layer. Within the present invention, by employing formed upon the planarizing passivation layer the dimensionally stabilizing layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.
The present invention provides a method for forming within a microelectronic fabrication a passivation layer passivating a bond pad, wherein the passivation layer is formed with enhanced and dimensionally stabilized planarization. The present invention realizes the foregoing object by employing when forming a microelectronic fabrication having formed therein a patterned conductor layer (which may be a bond pad) having at its periphery a topographic variation which is passivated with a planarizing passivation layer formed of a thermally reflowable material a dimensionally stabilizing layer formed upon the planarizing passivation layer such that upon thermally annealing the microelectronic fabrication and forming from the planarizing passivation layer a thermally annealed planarizing passivation layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials as are generally known in the art of microelectronic fabrication, but employed within the context of a specific process ordering to provide the present invention. Since it is thus a
Chen James
Cheu Eugene
Fahn Fu-Jier
Fan Gilbert
Lin Kenneth
Duong Khanh B.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
LandOfFree
Patterned conductor layer pasivation method with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Patterned conductor layer pasivation method with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Patterned conductor layer pasivation method with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3060688