Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2000-04-06
2002-02-05
Phasge, Arun S. (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S123000, C205S157000, C205S186000, C205S239000, C205S242000, C205S247000, C205S255000, C205S257000, C205S263000, C205S264000, C205S265000, C205S266000, C205S269000, C205S270000, C205S271000, C205S291000, C427S099300
Reexamination Certificate
active
06344125
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to metal plating processes and, more particularly, to a process for generating a patterned metal layer on an insulating substrate in the fabrication of semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
In the production of semiconductors, it is often necessary to form patterned metal layers on the semiconductor or insulator surface to provide conductive areas that transfer electrical current. Typically, such patterned layers are produced in one of two ways. One way is to use the desired pattern to form a mask and then to deposit the metal onto the dielectric or insulator in the desired pattern through the mask.
In the alternative, the metal is deposited as a continuous, un-patterned layer over the dielectric surface. The deposition of the continuous metal layer may be done in any one of a number of ways, including vacuum deposition, sputtering, and electrolytic or electroless plating, to name a few. The continuous metal layer is later selectively etched using a process such as photolithography, to generate a desired metal pattern. Photolithography is a process in which a light source illuminates a circuit pattern and projects the image through a lens assembly onto a semiconductor wafer or substrate. Ultimately, the circuit pattern is etched into the wafer.
All processes have advantages and disadvantages and some are better suited than others for a particular purpose. The need for circuits offering higher performance, which often means higher speeds, has resulted in a need for conductive elements with high conductivity so as to minimize losses. As a result, copper, with its high conductivity, has become a desirable metal to be used in integrated circuit applications replacing the traditional aluminum conductors.
Copper and copper alloys exhibit superior electromigration properties and have a lower resistivity than aluminum. Thus, copper and its alloys are useful in very large scale integration (VLSI) interconnect metallizations (i.e., more than 100,000 devices per chip). In addition, copper has improved electrical properties when compared to tungsten, making copper a desirable metal for use as a conductive plug as well as conductive wiring. There are also disadvantages, however, attendant upon the use of copper For example, copper readily diffuses through silicon dioxide, the typical dielectric interlayer material used in the manufacture of semiconductor devices, and adversely affects the devices.
From the manufacturing point of view, patterned copper or copper alloys are difficult to produce. For one, copper etching is problematic. Wet chemical etchants etch isotropically and generally permit insufficient dimensional control for sub-micron devices. Dry etching is typically used, but some metal layers, such as copper and gold, are difficult to plasma etch or reactive ion etch at reasonable production temperatures. During the chemical etching, the metal layer to be patterned is inevitably subjected to what is called “side etching” by an amount dependent upon the length of chemical etching, resulting in the patterned metal layer becoming smaller than the pattern of the mask layer by the amount of side etching. The amount of side etching depends upon the temperature, the flow rate, and other conditions of the etchant used; therefore, it is very difficult to predict the amount of side etching. The subtractive etching process is not currently used to form patterned layers of copper because of the difficulties associated with chemical and plasma etch processes.
When copper is used as the metal for conductors in a patterned metal layer, the typical process involves depositing a conformal barrier layer on the dielectric substrate, usually a tantalum layer, using chemical vapor deposition. The barrier layer prevents copper diffusion into the dielectric. Over the barrier layer there is next deposited a thin layer of copper metal to provide a seed layer having high conductivity. The coated substrate is placed next in a standard electrolytic bath and connected to a voltage source while a source of copper is also in the bath connected to the same voltage source. Uniform electrolytic deposition over the seed layer is accomplished by passing a current through the system.
This technique produces a uniform layer of copper over the seed layer with good adhesion to the barrier layer The photolithography and etching processes, with their related problems discussed above, are used to generate the desired conductive pattern. The deficiencies of the conventional processes show that a need still exists for a process for direct deposition of preferred metals patterned onto dielectric substrates without having to produce a continuous layer that is subsequently etched to form a desired pattern.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, the present invention provides a metal layer plating process that yields a patterned metal layer on an upper surface of a dielectric layer without masking or etching steps. More specifically, the present invention provides a process for controlling the electrolytic deposition of a first metal, such as aluminum, nickel, cobalt, silver, gold, palladium, platinum, rhodium, or copper; alloys of copper, of aluminum, of cobalt, of silver, of gold, of palladium, of platinum, of rhodium; and combinations of these metals and alloys, on a barrier layer comprising a refractory metal. The process comprises forming a first patterned conductive layer on a support, forming a dielectric layer over the support and conductive pattern, and forming a continuous barrier layer over the dielectric layer. The first patterned conductive layer may be an inductor, in the process of the present invention, or it may be a non-inductive conductive line pattern, such as a serpentine pattern. The process further comprises applying a current to the barrier layer while the barrier layer is immersed in an electrolytic bath.
Still more specifically, the process for forming a patterned metal layer on an upper surface of a dielectric layer comprises, according to the present invention, the following steps:
(a) forming a first conductive pattern on a substrate;
(b) forming a dielectric layer over the first conductive pattern and the substrate;
(c) forming a conformal barrier layer comprising a refractory metal on the upper surface of the dielectric layer; and
(d) electroplating directly on the barrier layer a metal selected from the group consisting of aluminum, nickel, cobalt, silver, gold, palladium, platinum, rhodium, or copper; alloys of copper, of aluminum, of cobalt, of silver, of gold, of palladium, of platinum, of rhodium; and combinations of those metals and alloys, by flowing a current through the barrier layer while immersing the barrier layer in an electroplating bath, the deposited metal forming a patterned layer during the deposition.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 4624749 (1986-11-01), Black et al.
patent: 5968333 (1999-10-01), Nogami et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5985125 (1999-11-01), Kim
patent: 5989623 (1999-11-01), Chen et al.
patent: 6004440 (1999-12-01), Hanson et al.
patent: 6020266 (2000-02-01), Hussein et al.
patent: 6024856 (2000-02-01), Haydu et al.
Locke Peter S.
Petrarca Kevin S.
Subbanna Seshadri
Volant Richard P.
International Business Machines - Corporation
Phasge Arun S,.
Ratner & Prestia
Schnurmann, E H. Daniel
LandOfFree
Pattern-sensitive electrolytic metal plating does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pattern-sensitive electrolytic metal plating, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern-sensitive electrolytic metal plating will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2975177