Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-07-05
2002-04-30
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S690000
Reexamination Certificate
active
06380633
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a pattern layout structure in substrate, and more particularly to a pattern layout structure in substrate that makes use of grid dummy pattern structure to improve the planarity and quality of the built-up substrate.
2. Description of Related Art
In the course of the development of the IC package technology, since the integration of the semiconductor is increasing and the chip design gradually tends toward functional integration, a lot of SOC (System On Chip) products are produced one after another. As a result, following the enhancement of the data processing capability, the numbers of the I/O (input/output) terminals required by the chip are getting more and more, and the size of the chip is increasing. Accordingly, in recent years, the number of IC package product having high density and high pin (or lead) count is increasing day by day.
Among the IC package products having high density and high pin (lead) count, the substrate type carrier is a package element frequently used. The substrate type carrier mainly includes two categories, that is, the pressed laminate type and the built-up type. As far as the flip chip substrate is concerned, the built-up substrate is the main stream of application. Generally, the built-up substrate is made by forming a multiplicity of insulative layers and patterned copper foil layers on the surface of the insulative core layer of the substrate wherein the insulative layer is formed by coating, and the material employed includes Epoxy, Polyimide etc. Since the insulative layer is formed by coating, the planarity of the copper foil layer on the top of the insulative layer is hard to be controlled. The non-controllable planarity of the copper foil layer will affect the photolithographic and etching quality of the copper foil layer, thereby, will lower the quality of the substrate, and in the mean time, will make the subsequent packaging process more difficult. Besides, in the light of the trend of the development of the semiconductor device, the required number of terminals of the substrate is gradually increased, so is the layout density and area of the substrate. Accordingly, the stress between layers becomes relatively large such that the manufacturing process of the substrate becomes relatively difficult.
FIG. 1
is a plan view of the patterned circuit layer according to a prior art. In the prior art technology, either the planarity of the copper foil layer or the stress between layers is closely related to the circuit layout of the copper foil layer. As shown in
FIG. 1
, the patterned circuit layer
102
in the built-up substrate
100
is formed by the use of a copper foil layer defined by the photolithographic and etching processes. The pattern layout includes a signal circuit region
104
, a power/ground region
108
, and the other region. The signal circuit region
104
has a multiplicity of conductive traces
106
disposed for signal transmission while the power/ground region
108
is for connecting to the power source and the ground. The other region of the copper layer is for forming dummy pattern region
110
for dissipating heat and avoiding electromagnetic interference.
FIG. 2
is the enlarged drawing of the power/ground and the dummy pattern region corresponding to those in
FIG. 1
according to the prior art. As shown in
FIG. 2
, the conventional power/ground region
108
and the dummy pattern region
110
are all constituted by a whole piece of copper foil with several ventilating holes
112
disposed thereon. As far as the current flip chip package substrate is concerned, the width of the conductive trace is around 40 &mgr;m, and the pitch is around 50~100 &mgr;m. Therefore, the fact that there is an obvious difference between the pattern density of the signal circuit region and that of the power/ground or the dummy pattern region will result in a non-uniform thickness in the subsequent process of coating the insulative layer. Accordingly, the planarity of the patterned circuit layer becomes worse. This will affect the quality of the substrate, and the planarity of the substrate will affect the yield of the subsequent packaging process. In addition, the copper foil pattern having relatively large area will result in a relatively high stress concentration, thereby, will lower the reliability of the substrate.
SUMMARY OF THE INVENTION
Therefore, it is one of the objectives of the present invention to provide a pattern layout structure of a substrate to make the pattern density uniform and to improve the planarity of the patterned circuit layer in the substrate.
It is another objective of the present invention to provide a pattern layout structure of a substrate that makes use of a grid pattern design to avoid the stress concentration so as to improve the quality and reliability of the substrate.
In order to attain the foregoing and other objectives, the present invention provides a pattern layout structure for package substrate. The pattern layout structure for package substrate includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers, wherein the patterned circuit layers are electrically connected to one another. The feature of the pattern layout is that the patterned circuit layer includes a signal circuit region, a power/ground region, and a dummy circuit region. The signal circuit region includes a multiplicity of conductive traces, and the power/ground region includes a first grid pattern while the dummy circuit region includes a second grid pattern. The first and second grid patterns are comprised of a plurality of first and second interlaced dummy traces, respectively. The pitch and the width of the first and second dummy traces are substantially equal to the pitch and the width of the conductive traces.
According to a preferred embodiment of the present invention, the patterned circuit layer is formed by the use of a copper foil layer through the processes defined by a photolithographic and etching process. Also, the first grid circuit and the second grid circuit include a grid circuit having 45-degree angle of inclination.
REFERENCES:
patent: 5886406 (1999-03-01), Bhansali
patent: 6165892 (2000-12-01), Chazan et al.
patent: 6171888 (2001-01-01), Lynch et al.
patent: 6198635 (2001-03-01), Shenoy et al.
patent: 6128731 (2001-04-01), Huang et al.
patent: 6225687 (2001-05-01), Wood
patent: 6246112 (2001-06-01), Ball et al.
J. C. Patents
Le Bau T
Nelms David
Siliconware Predision Industries Co., Ltd.
LandOfFree
Pattern layout structure in substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pattern layout structure in substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern layout structure in substrate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2931612