Pattern generator for memory burn-in and test

Details Pattern generator for memory burn-in and test Pattern generator for memory burn-in and test

1997-05-09

1999-12-21

Canney, Vincent P.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

G06F 1100

Patent

active

060063459

ABSTRACT:
A system and method for testing of a memory during burn-in is disclosed. In one aspect, the method and system include an address generator. The address generator includes a shift register means. The shift register includes n bit positions. The n bit positions are for storing n bits. The n bits are capable of being in a plurality of patterns. The address generator further includes a counter coupled to the shift register means. The counter includes a value that is incremented in response to a particular pattern of the plurality of patterns. The address generator has a complement mechanism coupled to the shift register and the counter which provides a complement of at least a portion of the n bits stored in the n bit positions in response to the value in the counter. In another aspect, the method and system comprise the address generator previously discussed coupled to the memory undergoing testing. In this aspect, the method and system further have a data generator coupled to the address generator and the memory and compare circuitry coupled to the memory and the data generator. In this aspect, a fail is detected when data from the data generator does not match data stored in the memory.

REFERENCES:
patent: 5506959 (1996-04-01), Cockburn
patent: 5606520 (1997-02-01), Gove et al.

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