Pattern generator

Details Pattern generator Pattern generator

1985-02-15

1987-06-02

Fleming, Michael R.

Excavating

371 25, G06F 1122

Patent

active

046708790

ABSTRACT:
In a main pattern memory are stored an increment command pattern and an enable control pattern in addition to test patterns. The main pattern memory is read out with an address from an address control circuit. The increment command pattern thus read out of the main pattern memory instructs incrementing of an address pointer, and a partial pattern memory is read out according to the contents of the address pointer. In accordance with the enable control pattern read out of the main pattern memory, a gate circuit is controlled to open, through which the output of the partial pattern memory is passed, and bits of the passed output are each ORed, by an OR circuit, with the corresponding bits of the test pattern read out of the main pattern memory, providing the ORed output as a test pattern.

REFERENCES:
patent: 3783254 (1974-01-01), Eichelberger
patent: 4287594 (1981-09-01), Shirasaka
patent: 4313200 (1982-01-01), Nishiura
patent: 4528634 (1985-07-01), Nakahata
patent: 4547861 (1985-10-01), Laviron
patent: 4550406 (1985-10-01), Neal
patent: 4555663 (1985-11-01), Shimizu
patent: 4571724 (1986-02-01), Belmondo

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