Pattern generation on a semiconductor surface

Details Pattern generation on a semiconductor surface Pattern generation on a semiconductor surface

2007-10-30

2007-10-30

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C700S097000, C700S120000, C700S121000, C430S005000, C378S035000

Reexamination Certificate

active

11091056

ABSTRACT:
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. A pattern on a reticle is first generated using a medium such as computer software to interconnect a number of active areas on the wafer. The pattern is then modified according to a number of rules to create a pattern where substantially all spaces between planned elements exhibit a desired gap width. Layers of elements such as trace lines can be better covered with an ILD in a simplified deposition process as a result of the novel pattern formation described herein.

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Juengling, Werner, “Method and Apparatus for Designing a Pattern on a Semiconductor Surface”, Pending U.S. Appl. No. 10/931,361, filed Aug. 31, 2004.

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