Pattern generating apparatus

Details Pattern generating apparatus Pattern generating apparatus

1998-05-21

2000-11-14

Cady, Albert De

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

G11C 2900

Patent

active

061484245

ABSTRACT:
A pattern generating apparatus used in quality judgment testing of memories incorporating a predetermined signal transfer configuration such as a protocol transfer system, the apparatus having: an address generating device for sequentially generating address patterns for specifying storage regions in a test memory; a first control device for converting the sequentially generated address patterns into a signal transfer configuration for the test memory and supplying these to the test memory to sequentially access the storage regions specified by the respective address patterns; and a second control device for determining a condition in which the test memory is operated with respect to the address pattern generated by the address generating device, and controlling a generation timing for the address pattern based on this.

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