Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-15
2009-11-03
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07614026
ABSTRACT:
A pattern of a desired size is formed on a semiconductor substrate by the following procedure. A property, including at least one of an aberration of an exposure device, a property of an illumination, a property of a projection lens, and a pattern coverage in a shot, are allocated, in a first database, to predetermined positions assigned in a chip. A second database is prepared by pairing a cell name of a cell extracted from hierarchical processing of a design pattern and arrangement positional data of the cell. The property data is allocated to the cell based on the first and second databases. Mask data processing based on at least one of the property data is executed, and the cell subjected to the mask data processing is rearranged on the chip.
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Notice of Examination Opinion dated Jul. 15, 2009, from the Taiwanese Patent Office in Taiwan Application No. 095132752, and English-language translation of same.
Ichikawa Hirotaka
Kotani Toshiya
Dinh Paul
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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