Pattern forming method, computer program thereof, and...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07614026

ABSTRACT:
A pattern of a desired size is formed on a semiconductor substrate by the following procedure. A property, including at least one of an aberration of an exposure device, a property of an illumination, a property of a projection lens, and a pattern coverage in a shot, are allocated, in a first database, to predetermined positions assigned in a chip. A second database is prepared by pairing a cell name of a cell extracted from hierarchical processing of a design pattern and arrangement positional data of the cell. The property data is allocated to the cell based on the first and second databases. Mask data processing based on at least one of the property data is executed, and the cell subjected to the mask data processing is rearranged on the chip.

REFERENCES:
patent: 6374396 (2002-04-01), Baggenstoss et al.
patent: 6706456 (2004-03-01), Miyashita et al.
patent: 2003/0005390 (2003-01-01), Takashima et al.
patent: 2003/0088839 (2003-05-01), Watanabe
patent: 2006/0143589 (2006-06-01), Horng et al.
patent: 2006/0245636 (2006-11-01), Kitamura et al.
patent: 2005-24903 (2005-01-01), None
patent: 459348 (2001-10-01), None
patent: 490591 (2002-06-01), None
Notice of Examination Opinion dated Jul. 15, 2009, from the Taiwanese Patent Office in Taiwan Application No. 095132752, and English-language translation of same.

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