Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-18
2002-08-13
Everhart, Caridad (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06434730
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a layout pattern for a semiconductor device including cells and bypass capacitors with an MOS structure.
As the operating frequency of a present-day LSI has been increasing, a ratio of noise to signal has also been rising in transistors within the LSI. To eliminate the noise as much as possible, various techniques have been proposed.
According to an exemplary noise reduction technique, a bypass capacitor is placed between power and ground lines to cut down the noise component of the power supply.
However, a technique of placing a bypass capacitor at an appropriate location has not been established yet in fabricating a semiconductor device following a pattern that has been created in advance by some physical design technique using basic cells, for example. Thus, there is a strong demand for a method of creating an optimum pattern for a semiconductor device automatically while taking not only noise, but also various characteristics of the device, such as the number of devices integrated per unit area, into account.
SUMMARY OF THE INVENTION
An object of the present invention is providing a method of defining an optimum layout pattern automatically, which is best suited to a miniaturized, noise-reduced semiconductor device, to cope with everlasting downsizing and tremendous increase in operating frequency of semiconductor devices.
An inventive pattern forming method is adapted to form a layout pattern for a semiconductor device automatically. The method includes the steps of: a) defining a layout, which includes a pattern for a cell with an MIS structure and patterns for power and ground lines, over a semiconductor substrate; and b) automatically creating patterns for bypass capacitors with an MIS structure such that the patterns for the capacitors overlap with the pattern for the power line. Each said bypass capacitor includes the semiconductor substrate, a capacitive insulating film and an electrode.
According to this method, the pattern for the power line has already been created before the patterns for the bypass capacitors are defined. Thus, the patterns for the bypass capacitors can be defined automatically so as to be included in the pattern for the power line. That is to say, a densely integrated and noise-reduced semiconductor device can be fabricated based on automatically created patterns.
In one embodiment of the present invention, a pattern for a first diffused layer, which is provided on right- and left-hand sides of the electrode, may be included in the pattern for each said bypass capacitor. And the ground line may be connected to a second diffused layer in the semiconductor substrate via substrate contacts. In this particular embodiment, the method preferably further includes the step of c) creating a pattern for a third diffused layer interconnecting the first diffused layer of the bypass capacitors and the second diffused layer together.
In this method, the pattern for the first diffused layer is included in the pattern for each bypass capacitor. Accordingly, it is possible to recognize the bypass capacitor as an equivalent to an MIS transistor in the cell, thus facilitating the automated pattern formation process. In addition, since the ground line is connected to the second diffused layer in the semiconductor substrate via the substrate contacts, a pattern for a structure including a highly latch-up resistant cell can be obtained. Moreover, by defining the pattern for the third diffused layer, the bypass capacitors, along with the low-resistance diffused layer, can be interposed between the power and ground lines. That is to say, a pattern obtained in this manner is applicable to fabricating a semiconductor device that can greatly reduce unwanted radiative noise involved with radio frequency operation.
In an alternate embodiment, the step b) may include the sub-steps of: x) preparing a pattern for an array of bypass capacitors; y) extracting the pattern for the power line from the layout; and z) superimposing the pattern for the power line on the pattern for the bypass capacitor array and extracting, as the patterns for the bypass capacitors, part of the pattern for the bypass capacitor array that overlaps with the pattern for the power line. In this manner, automated pattern formation process can be simplified.
In this particular embodiment, patterns for two types of bypass capacitor arrays may be prepared in the sub-step x). Each of the patterns may be in the form of a rectangle where the electrodes of the bypass capacitors extend in a predetermined direction. And the direction in which the electrodes extend in one of the two patterns may cross at right angles with the direction in which the electrodes extend in the other pattern. In this case, the patterns for the bypass capacitors may be defined in the sub-step z) such that the electrodes of the bypass capacitors are parallel to the power line.
In an alternative embodiment, patterns for two types of bypass capacitor arrays may also be prepared in the sub-step x). Each of the patterns may be in the form of a rectangle where the electrodes of the bypass capacitors extend in a predetermined direction. And the direction in which the electrodes extend in one of the two patterns may cross at right angles with the direction in which the electrodes extend in the other pattern. In this case, the patterns for the bypass capacitors may be defined in the sub-step z) by rotating the bypass capacitors in such a direction as maximizing the area of an interconnecting diffused layer.
In another alternative embodiment, a single pattern for the bypass capacitor array may be prepared in the sub-step x). The pattern may be in the form of a rectangle where the electrodes of the bypass capacitors extend in a predetermined direction. In this case, the patterns for the bypass capacitors may be defined in the sub-step z) such that the electrodes of some of the bypass capacitors are parallel to the power line and the electrodes of the other bypass capacitors cross at right angles with the power line.
In still another embodiment, each said electrode may be ringlike, and the first diffused layer may exist in a region surrounded by the electrodes and in a region outside of the electrodes in the pattern prepared in the sub-step x) for the bypass capacitor array. In this manner, bypass capacitors of the same shape can be placed irrespective of the direction in which the power lines extend.
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Ito Mitsumi
Kojima Seijiro
Sawada Masatoshi
Tsujikawa Hiroyuki
Everhart Caridad
Levin Naum
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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