Pattern forming method

Details Pattern forming method Pattern forming method

1990-08-27

1991-12-24

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156651, 156656, 156657, 1566591, 156662, 437 41, 437233, 437245, H01L 21306, B44C 122, C03C 1500, C23F 102

Patent

active

050749560

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
This invention relates to a method for forming a pattern of a film made of a desired material on a side wall of a stepped base, which pattern formation method is appropriately used, for example, for forming a desired film pattern of good precision on a plane which extends orthogonally to the main plane of the base in order to achieve high integration of an LSI.
2. Description of the Related Art
In order to improve the degree of integration of an LSI over a limited substrate area, the reduction of areas over which individual semiconductor elements constituting the LSI are defined on the main plane of the substrate has become more and more necessary. To this end, a technique has been employed wherein a groove is made in the substrate so that the side walls (portions corresponding to wall surfaces) are utilized as regions for forming semiconductor elements in order to provide an increased surface area over which the elements can be formed. However, the side walls defining such grooves have only been used, for example, to accommodate capacitor elements and have never been used to form a wiring pattern or a gate electrode of a transistor. Nevertheless, the necessity for forming a wiring pattern or elements on the side wall will be more and more in demand, and so it is believed to be necessary to establish a method wherein a wiring pattern or a gate electrode can be readily formed.
FIG. 5 illustrates a thin film pattern on a side wall, and is a perspective view of an ideal form of a thin film pattern. In this case, a semiconductor substrate 13 has a groove 11 with a depth l, and the thin film pattern 17 extends on a side wall 15 defining the groove 11 along the depth l of the groove 11.
However, it is very difficult to form such an ideal thin film pattern 17 as shown in FIG. 5.
FIGS. 6(A)-(C) illustrate main steps used to form a film pattern on a side wall according to a pattern forming method using the known single layer resist process. More particularly, FIGS. 6(A) and (C) are, respectively, partial perspective views taken in the direction P shown in FIG. 5, and FIG. 6(B) is a plan view of the sample shown in FIG. 6(A).
When the single resist process is used, a film 21 of material used to form a thin film pattern is formed on the surface of the semiconductor substrate 13 including over the inner surfaces thereof defining the groove 11. Next, the film material 21 is coated over the entire surface thereof, for example, with a positive resist (not shown). Subsequently, a light-shielding mask is provided at such a position that it crosses a boundary 11a of the step established by the groove 11, the resist is exposed to light irradiated from above the light-shielding mask, and the resist is developed to form a resist pattern 25 on a region traversing the boundary 11a of the step (FIG. 6(A)). However, the thus formed resist pattern 25 has a shape which is completely different from the shape of the light-shielding mask 23 as is particularly shown in FIG. 6(B). The reason for this is that the resist which has been applied over the surface of the semiconductor substrate 13 is thicker at the bottom portion of the groove and particularly at the corner portions of the groove 11, so that the exposure light does not reach the lower side of the thicker portion of the resist. Accordingly, a thin film pattern 21a which is obtained by an anisotropic etching technique, such as RIE (Reactive Ion Etching), has a shape which is far different from the shape of the light-shielding mask 23 as is shown in FIG. 6(C). More particularly, a useless region as shown in FIG. 6(C) as hatched is left at the lower portion of the step.
As a measure for overcoming the drawback involved in the known single layer resist process, there was known a so-called double layer resist process disclosed, for example, in "Process Techniques For Next Generation Super LSI," Applications, Apr. 4, 1988, by Realize Co., Ltd., (pp. 297-298). In this process, after the step of the substrate is filled in with a fi

REFERENCES:
"Practicing the Novolac deep-UV portable conformable masking technique", B. L. Lin, E. Bassous, V. W. Chao, & K. E. Petrillo, J. Vac. Sci. Technol., 19(4), Nov./Dec. 1981, pp. 1313-1319.
VLSI Technology, 7.6.2 Multilevel Resists, pp. 294-296.

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