Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-04-19
2005-04-19
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S108000, C438S622000, C438S625000, C438S666000, C438S667000, C438S623000
Reexamination Certificate
active
06881662
ABSTRACT:
A pattern formation process for an integrated circuit substrate, which is not employing the conventional method of filling resin material directly in via filling process but adapting the metal spray method, the metal vapor deposition method or any combination thereof to form the pattern including circuits and pads and stuff the vias and the through holes.
REFERENCES:
patent: 5118385 (1992-06-01), Kumar et al.
patent: 5122227 (1992-06-01), Ott
patent: 5382315 (1995-01-01), Kumar
patent: 5877076 (1999-03-01), Dai
patent: 5891527 (1999-04-01), Turek et al.
patent: 6163957 (2000-12-01), Jiang et al.
patent: 6521533 (2003-02-01), Morand et al.
patent: 6640434 (2003-11-01), Wojewnik et al.
patent: 20030203705 (2003-10-01), Leng
Ho Kwun-Yao
Kung Moriss
Anya Igwe U.
Smith Matthew
Via Technologies Inc.
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