Pattern detection for computer segments

Details Pattern detection for computer segments Pattern detection for computer segments

2001-09-14

2004-04-20

Chung, Phung M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S799000, C714S746000

Reexamination Certificate

active

06725420

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to pattern detection in a sequence of computer marks and spaces.
BACKGROUND OF THE INVENTION
At present, a FIFO or similar device is used to store information about mark and space lengths. An error that occurs in such information will propagate and affect other device information downstream of the location where the error occurs.
What is needed is an approach that provides mark and space information but does not permit an error in such information to propagate much beyond the location where the error is first observed.
SUMMARY OF THE INVENTION
These needs are met by the invention, which provides a system that compares mark and space information immediately before a segment is received by a segment processor. Three consecutive segments, MK, PS and PM, are received by segment pre-processors, and the segment lengths, L(MK), L(PS) and L(PM), are determined. If one or another of these lengths is non-complying, the corresponding pre-processor optionally issues an error signal that is received by the processor before, or at the time that, the processor receives at least one of these three segments. The processor then compensates for, or corrects, a segment with a non-complying length.


REFERENCES:
patent: 5047919 (1991-09-01), Sterling et al.

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