Pattern delineation of vertical load resistor

Details Pattern delineation of vertical load resistor Pattern delineation of vertical load resistor

1986-10-23

1987-09-01

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29610R, 29620, 156646, 156653, 156657, 1566591, 156662, 20419232, 338308, 427103, H01L 21306, B44C 122, C23F 102, C03C 1500

Patent

active

046907289

ABSTRACT:
A process for delineating a vertical resistor on a semiconductor device is disclosed. Resistive and diffusion barrier layers are deposited and then etched, first by dry plasma and then by wet bath. The two step etching allows complete removal of the deposited layers with minimal damage to exposed dielectric, silicide, polysilicon or doped regions on the semiconductor.

REFERENCES:
patent: 3900944 (1975-08-01), Fuller et al.
patent: 4208781 (1980-06-01), Rao et al.
patent: 4341594 (1982-07-01), Carlson et al.
patent: 4445966 (1984-05-01), Carlson et al.
Ghandhi, "VLSI Fabrication Principles", A Wiley-Interscience Publication 1983, pp. 427-429.
Adams, "VLSI Technology", 1983, McGraw Hill, pp. 120-123.

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