Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-07-08
2004-09-07
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06789250
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2001-206541 filed on Jul. 6, 2001; the entirety of which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pattern data generation system for LSI masks using a computer, a pattern data generation method, a pattern data generation program, and a method of manufacturing semiconductor devices using the pattern data. In particular, it is related to a computer aided mask pattern data generation system for generating master mask pattern data for a photo-repeater; a computer aided mask pattern data generation method; a mask pattern data generation program for controlling the computer aided mask data generation system; a method of fabricating reticles using this master mask, and moreover, a method of manufacturing semiconductor devices using the above.
2. Description of the Related Art
A glass mask (4× magnified mask), or a reticle, that is drawn at 4× magnification relative to the size of the pattern that is to be formed on the actual silicon chip is used during a lithography process used in the LSI manufacturing process. More specifically, after fabricating a set of reticle with a pattern generator, using an exposure system, or a stepper, each of the intended circuit patterns delineated on the reticle is ¼ reduced and transferred onto the silicon wafer. With this lithography method, given that cutting edge LSI design rules at present have become miniaturized to 0.1 &mgr;m or lower, even with the architecture of the 4× mask, highly accurate minute pattern generation has become difficult. As a result, an exceedingly expensive electron beam lithography (EBL) system must be used as the pattern generator used for 4× mask fabrication, which has lead to problems such as the price of masks becoming extremely high.
Therefore, with the aim of breaking through current limits of microfabrication while keeping mask fabrication costs to a minimum, techniques have been proposed to fabricate a master mask, which is a 5× magnification of the 4× mask. The 5× magnification mask can be fabricated with a low-cost popular pattern generator. In other words, a technique reduces this 5× master mask by ⅕ and transferring the image onto a mask substrate. In this case, an exposure system called a photo-repeater is used for pattern generation upon the mask substrate of the conventional 4× mask. The introduction of a photolithographic method using a reticle formed with this photo-repeater into LSI manufacturing methods is being studied. With the above-mentioned photo-repeater, it becomes possible for the master mask used by the photo-repeater to handle mask layout data with 20× (4××5×) magnification of the actual pattern ultimately applied onto the silicon chip. As a result, even if the design rule for the pattern upon the silicon chip was to be, for example, approximately 0.1 &mgr;m, the processing of approximately 2 &mgr;m can be employed on the master mask to be fabricated. Since the use of a high cost EBL system becomes unnecessary, the problem of microfabrication limits of the pattern generator is avoided. More specifically, since accommodation may be made with a common optical pattern generator due to the significant relaxation of the master mask pattern design rules, reduction in the cost per unit for one reticle is expected.
However, with the above-mentioned photo-repeater, the pattern region of the master mask becomes larger and has an inverse relationship with the reduction ratio. More specifically, when fabricating a master mask with the magnification of 5×, if the pattern region of the reticle is simply divided up, then 5×5=25 master masks become fabricated. And as a result, there are no longer any cost merits. As a result, while means for reducing the number of master masks fabricated have come to be implemented due to worker ingenuity; problems have developed such as the number of master masks fabricated fluctuating and fabrication errors developing due to differences in worker skill.
In addition, in the case where experimental generation results have made design changes necessary, a refined mask (corrected mask) becomes necessary for the redesigned LSI. When fabricating this refined mask, the coordinate values for the redesigned layout data are given to the worker; the worker then finds the pertinent master mask from the coordinate values and refabricates that pertinent master mask. As a result, problems such as increased labor and fabrication errors develop.
Moreover, the refined mask fabrication described above has been carried out with a method that involves refabrication of a master mask having newly pattern layout data that is a combination of only the corrected layout data and the original version of the design data and fabricating only a minimum number of master masks. However, there have been problems with such a method such as the number of master masks used increasing and the operating time of the photo-repeater becoming longer with each subsequent time correction made due to the fact that new configurations of the pattern layout data for the master mask are generated every time corrections develop. In addition, there are further problems such as management of the master masks used becoming difficult.
SUMMARY OF THE INVENTION
A first aspect of the present invention is to provide a pattern data generation system, which includes a) a chip division information storage unit configured to register chip division information of how a chip is divided so that pattern data of enlarged reticle chip pattern data fit into a master mask pattern region; b) a chip layout generation unit configured to generate master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns configuring the chip division information; c) a master mask chip layout information storage unit configured to register the master mask chip layout information; d) a chip pattern data generation unit configured to generate master mask chip pattern data by referencing the reticle chip pattern data and divide each chip in accordance with the master mask chip layout information; e) a master mask pattern data information storage unit configured to register the master mask chip pattern data; and f) a pattern data generation unit configured to generate master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data.
A second aspect of the present invention provides a pattern data generation method, which includes a) generating chip division information by performing division processing of a chip pattern so that pattern data of enlarged reticle chip pattern data fit into a master mask pattern region; b) registering the chip division information in a chip division information storage unit; c) generating master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns configuring the chip division information; d) registering the master mask chip layout information in a master mask chip layout information storage unit; e) generating master mask chip pattern data by referencing the chip pattern data for the reticle and dividing each chip in accordance with the master mask chip layout data; f) registering the master mask chip pattern data in a master mask pattern data information storage unit; and g) generating master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data.
A third aspect of the present invention provides a pattern data generation program for controlling a pattern data generation system. This program is embraces a) a command for generating chip division information by dividing a chip pattern into
Watanabe Susumu
Yano Mitsuhiro
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Whitmore Stacy A.
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