Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-07-02
2008-11-25
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07458057
ABSTRACT:
According to an aspect of the invention, there is provided a pattern correction method in which a shape of a target pattern is corrected in accordance with an arrangement state between the target pattern configuring a designed pattern and a vicinity pattern disposed in the vicinity of the target pattern, the pattern correction method comprises detecting a first arrangement state between a first predetermined portion of an edge of the target pattern and the vicinity pattern, detecting a second arrangement state between a second predetermined portion of the edge of the target pattern and the vicinity pattern, determining a correction value of the edge of the target pattern based on a rule in accordance with the first and second arrangement states, and adding the correction value to the edge of the target pattern.
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Notification of First Office Action from the SIPO of the People's Republic of China, mailed Apr. 28, 2006, in Chinese Patent Application No. 2004-100500846, and English translation thereof.
Notification of Reasons for Rejection from the Japan Patent Office, mailed Oct. 23, 2007, in Japanese Patent Application No. 2003-190341, and English translation thereof.
Chiang Jack
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Tat Binh C
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