Pattern and method for measuring alignment error

Details Pattern and method for measuring alignment error Pattern and method for measuring alignment error

1997-07-24

1999-01-19

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257797, 257207, 257211, H01L 23544

Patent

active

058616799

ABSTRACT:
An alignment error measurement pattern includes a plurality of wiring patterns and a plurality of opening patterns formed in an insulating film covering the wiring patterns. The edges of the wiring patterns and the opening patterns correspond to each other to constitute sets, and distances between them are all different from one set to another. Corresponding wiring pattern and opening pattern in the same set are or are not in contact with each other depending on the alignment error between them. Therefore, the alignment error between the wiring pattern and the opening pattern can be electrically measured by checking the conduction state between them. Hence, an alignment error of a semiconductor device can be measured at high precision, and easily even after the manufacture.

REFERENCES:
patent: 5384488 (1995-01-01), Golshan et al.
patent: 5625224 (1997-04-01), Greenwood et al.

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