Path memory circuit

Details Path memory circuit Path memory circuit

2004-12-07

2010-06-08

Rizk, Sam (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C704S242000, C375S262000

Reexamination Certificate

active

07734992

ABSTRACT:
A path memory circuit for use in a Viterbi decoding process performed based on state transitions through a number n (n is a positive integer) of states. The path memory circuit includes a memory area A formed by the storage circuits of the first to ith(i is an integer from 0 to M) stages; a memory area B formed by the selective storage circuits that select and hold a decoding result for any state k (k is integer from 1 to n) of the storage circuits from the i+1thstage to the Mthstage; and a memory area C formed by the selective storage circuits other than the memory area A and the memory area B.

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