Path memory apparatus of a viterbi decoder

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H03M 1312

Patent

active

054467462

ABSTRACT:
The path memory apparatus of a Viterbi decoder having an add-compare-select circuit for producing path select signals and a minimum state number every symbol period comprises a first selector for selecting between the path select signals and feedback signals in accordance with a start clock; a memory for receiving the output of a first selector and shifting the received output thereof in one direction in accordance with a system clock, and applying the output as the feedback signal; a second selector for selecting one among the outputs of the memory in accordance with a current state number; a third selector for selecting between the minimum state number and a next state number in accordance with the start clock, to produce the current state number; a trace-back calculator for receiving the current state number and the output of second selector and then producing the next state number; and a data convertor for performing an operating on the next state numbers, to produce a decoded information symbol per each symbol period.

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patent: 4748626 (1988-05-01), Wong
patent: 4777636 (1988-10-01), Yamashita et al.
patent: 4905317 (1990-02-01), Suzuki et al.
patent: 5220570 (1993-06-01), Lou et al.
patent: 5257263 (1993-10-01), Bazet et al.

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