Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-10
2005-05-10
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06892368
ABSTRACT:
Automated patching techniques to correct certain rule violations are used, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit. A series of patches of predefined orientations are utilized to correct design rule violations. A set of violations are identified, patches of a predefined orientation are attempted to correct one or more violations. Patches of another predefined orientation are attempted to correct remaining violations. Attempted patching is repeated until all patches in the series have been attempted or all violations have been corrected. Patches can be added to a construction layer over the set of violations, and each patch that does not cause a design rule violation can be copied to a metal layer. A series of patches of predefined orientations are used, efficiently correcting design rule violations such as minimum area and jog rule violations.
REFERENCES:
patent: 5620916 (1997-04-01), Eden et al.
patent: 5689435 (1997-11-01), Umney et al.
patent: 5706295 (1998-01-01), Suzuki
patent: 5798937 (1998-08-01), Bracha et al.
patent: 5926723 (1999-07-01), Wang
patent: 5970238 (1999-10-01), Shibata et al.
patent: 6011911 (2000-01-01), Ho et al.
patent: 6026224 (2000-02-01), Darden et al.
patent: 6063132 (2000-05-01), DeCamp et al.
patent: 6078737 (2000-06-01), Suzuki
patent: 6189136 (2001-02-01), Bothra
patent: 6209123 (2001-03-01), Maziasz et al.
patent: 6275971 (2001-08-01), Levy et al.
patent: 6301686 (2001-10-01), Kikuchi et al.
patent: 6324673 (2001-11-01), Luo et al.
patent: 6370679 (2002-04-01), Chang et al.
patent: 6374395 (2002-04-01), Wang
patent: 6378110 (2002-04-01), Ho
patent: 6446873 (2002-09-01), Geryk
patent: 6457163 (2002-09-01), Yang
patent: 6461877 (2002-10-01), Holloway et al.
patent: 6484302 (2002-11-01), Freymuth
patent: 6487706 (2002-11-01), Barkley et al.
patent: 6536023 (2003-03-01), Mohan et al.
patent: 6606735 (2003-08-01), Richardson et al.
patent: 6611946 (2003-08-01), Richardson et al.
patent: 6615400 (2003-09-01), Lukanc
patent: 6637013 (2003-10-01), Li
patent: 6718527 (2004-04-01), Li
patent: 6775806 (2004-08-01), Li
patent: 20020127479 (2002-09-01), Pierrat
patent: 20020174413 (2002-11-01), Tanaka
patent: 20030061583 (2003-03-01), Malhotra
patent: 20030088843 (2003-05-01), Mehrotra et al.
patent: 20030182644 (2003-09-01), Li et al.
patent: 20030196180 (2003-10-01), Li et al.
patent: 20030229860 (2003-12-01), Li
patent: 20030229862 (2003-12-01), Li et al.
patent: 20040019862 (2004-01-01), Li et al.
patent: 20040019866 (2004-01-01), Li
patent: 20040019867 (2004-01-01), Li
patent: 20040019868 (2004-01-01), Li
patent: 20040025125 (2004-02-01), Li
patent: 20040063228 (2004-04-01), Li et al.
patent: 20040064795 (2004-04-01), Li et al.
patent: 20040064796 (2004-04-01), Li
patent: 20040064797 (2004-04-01), Li
Yu Chen et al., “Hierarchical Dummy Fill for Process Uniformity,” Proc. Asia and South Pacific Design Automation Conf, Jan. 2001, pp. 139-144.
Andrew B. Kahng et al., “Filling Algorithms and Analyses for Layout Density Control,” IEEE Trans. Computer Aided Design 18(4) (1999) pp. 445-462.
Barnes, “Skill: A CAD System Extension Language,” 1990 27thACM/EEE Design Automation Conference, pp. 266-271.
Karam et al., “High Level CAD Melds Microsystems with Foundries,” 1996 European Design and Test Conference, pp. 442-447.
Luo et al., “An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking,” 1999 7thAnnual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 158-167.
Diva Verification, http://www.cadence.com/datasheets/diva.html 2002 Cadence Design Systems, Inc., downloaded May 17, 2002, 3 pages.
Li Mu-Jing
Yang Amy
Whitmore Stacy A.
Zagorin O'Brien Graham LLP
LandOfFree
Patching technique for correction of minimum area and jog... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Patching technique for correction of minimum area and jog..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Patching technique for correction of minimum area and jog... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3427921