Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2005-11-08
2010-06-15
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S103000, C711S170000, C717S168000
Reexamination Certificate
active
07739469
ABSTRACT:
An instruction set is executed from Read Only Memory (ROM). When a current instruction in the instruction set corresponds to a reserved patch memory block of ROM, a Random Access Memory (RAM) index and a ROM return address are loaded into a memory map, and a program counter is set to a first reserved ROM address. After jumping the program counter to the first reserved ROM address, the program counter is jumped to RAM based on the RAM index to execute a patch code, which includes at least one instruction to set the program counter to a second reserved ROM address. When the program counter equals the second reserved ROM address, the ROM return address is retrieved. Then the instruction set is executed from ROM based on the ROM return address.
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Sherwood, T. and Calder, B. 2001. Patchable instruction ROM architecture. In Proceedings of the 2001 international Conference on Compilers, Architecture, and Synthesis For Embedded Systems (Atlanta, Georgia, USA, Nov. 16-17, 2001). CASES '01. ACM, New York, NY, 24-33.
Baker David
Jessani Romesh Mangho
Koelling Robert
Torrini Antonio
Dillon Samuel
Freescale Semiconductor Inc.
Shah Sanjiv
Stanford Gary R.
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