Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2007-08-07
2007-08-07
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C257SE21568
Reexamination Certificate
active
10501522
ABSTRACT:
A plurality of recessed portions having different depths is formed in a surface of the active layer wafer or in a bonding surface of the supporting substrate wafer. Those wafers are bonded to each other with an insulation film interposed therebetween. This allows a cavity of higher dimensional precision to be buried therein. A plurality of cavities may be formed simultaneously in a plurality of locations within the plane of the substrate, which allows the thickness of the SOI layer to be set arbitrarily. Accordingly, such a semiconductor device can be fabricated easily in which a MOS type element and a bipolar element are formed on the same chip in a mixed manner.
REFERENCES:
patent: 3902936 (1975-09-01), Price
patent: 5091330 (1992-02-01), Cambou et al.
patent: 5238865 (1993-08-01), Eguchi
patent: 5313092 (1994-05-01), Tsuruta et al.
patent: 5346848 (1994-09-01), Grupen-Shemansky et al.
patent: 5804086 (1998-09-01), Bruel
patent: 5804495 (1998-09-01), Saito et al.
patent: 6060344 (2000-05-01), Matsui et al.
patent: 6114197 (2000-09-01), Hsu
patent: 6124185 (2000-09-01), Doyle
patent: 6191007 (2001-02-01), Matsui et al.
patent: 6534380 (2003-03-01), Yamauchi et al.
patent: 6613652 (2003-09-01), Lim et al.
patent: 6660564 (2003-12-01), Brady
patent: 6673694 (2004-01-01), Borenstein
patent: 6759282 (2004-07-01), Campbell et al.
patent: 6809009 (2004-10-01), Aspar et al.
patent: 6841861 (2005-01-01), Brady
patent: 6958255 (2005-10-01), Khuri-Yakub et al.
patent: 2002/0190319 (2002-12-01), Borenstein
patent: 2004/0070032 (2004-04-01), Mori et al.
patent: 2004/0113228 (2004-06-01), Yamada et al.
patent: 0 191 476 (1986-08-01), None
patent: 1 213 748 (2002-06-01), None
patent: 9-135030 (1997-05-01), None
patent: 11-145481 (1999-05-01), None
patent: 2001-144276 (2001-05-01), None
patent: 1998-69868 (1998-10-01), None
Adachi Naoshi
Nakamae Masahiko
Isaac Stanetta
Kubovcik & Kubovcik
Lebentritt Michael
Sumitomo Mitsubishi Silicon Corporation
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