Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-12-08
2002-02-26
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C326S086000, C327S112000, C327S170000
Reexamination Certificate
active
06351136
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital systems, and more particularly to controlling noise signals in digital systems.
BACKGROUND
In the transmission of signals, a mismatch between a transmission line impedance and a receiver impedance can result in overshoot and undershoot noise. The presence of overshoot and undershoot noise in a digital system degrades the insulating properties of the oxide layers of active termination circuits, and after a certain amount of degradation the termination circuits fail.
FIG. 1A
is a schematic diagram of prior art circuit
100
for receiving and transmitting digital signals. Transistor
106
is capable of driving signals onto a transmission line coupled to pad
103
. Active termination circuit
109
including transistor
112
provides an active pull-up for receiving signals at pad
103
. One disadvantage of prior art circuit
100
is that for signals that include overshoot or undershoot noise at pad
103
, the gate-to-drain voltage
115
of transistor
112
is greater than the difference between source supply voltage V
TT
and the output low voltage V
OL
. The repeated application of this increased voltage across the gate and drain of transistor
112
stresses the gate oxide layer, causes the performance of transistor
112
to degrade, and eventually causes transistor
112
to fail.
FIG. 1B
is an illustration of undershoot noise in digital signal waveform
118
. Voltage
121
is the voltage applied between the gate and drain of transistor
112
as a result of the undershoot noise voltage. Voltage
124
is the voltage applied between the gate and drain of transistor
112
after the undershoot noise settles out. Voltage
121
is greater than voltage
124
and the repeated application of voltage
121
between the gate and drain of transistor
112
causes the insulating properties of the gate oxide of transistor
112
to degrade.
FIG. 1C
is a block diagram of prior art system
127
for suppressing overshoot and undershoot noise in a digital system.
FIG. 1C
shows prior art system
100
shown in
FIG. 1A
coupled to edge detect and timer circuit
130
and transistors
133
and
136
. Transistors
133
and
136
are coupled to pad
103
. In operation, edge detect and timer circuit
130
turns on transistor
133
or transistor
136
to suppress overshoot and undershoot noise at pad
103
. Whenever a rising edge is detected at pad
103
, transistor
136
is turned on for a predetermined period of time to clamp the overshoot noise level. Similarly, whenever a falling edge is detected, transistor
133
is turned on for a predetermined period of time to clamp the undershoot noise level.
Unfortunately, not all overshoot and undershoot noise coincides with a rising or falling edge at pad
103
. For example, some overshoot and undershoot noise results from the coupling of switching transients from neighboring lines to transmission lines coupled to pad
103
. These transients are not suppressed by edge detect and timer circuit
130
. A second problem with edge detect and timer circuit
130
is that transistors
133
and
136
, typically n-type metal-oxide semiconductor (n-MOS) and p-type metal-oxide semiconductor (p-MOS) transistors, respectively, require a large amount of chip real estate near pad
103
, which decreases the amount of real estate available for information processing circuits. Still another problem with edge detect and timer circuit
130
is that accurate timing of the clamping function is critical to successful operation of the circuit. Releasing the clamping too early results in over voltage or under voltage noise on the signal line, and holding the clamping too long reduces the data rate on the signal line.
For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
A circuit comprises an active termination device for pulling up an interconnect node, a transistor for driving the interconnect node, and a passive voltage limiter coupled to the interconnect node. The passive voltage limiter also couples the transistor to the active termination device.
REFERENCES:
patent: 4748426 (1988-05-01), Sewart
patent: 5654860 (1997-08-01), Casper et al.
patent: 5654981 (1997-08-01), Mahant-Shetti et al.
patent: 5801563 (1998-09-01), McClure
patent: 5811984 (1998-09-01), Long et al.
patent: 5819099 (1998-10-01), Ovens
patent: 5936429 (1999-08-01), Tomita
patent: 6043702 (2000-03-01), Singh
patent: 6046653 (2000-04-01), Yamada
patent: 6084432 (2000-07-01), Dreps et al.
patent: 6133755 (2000-10-01), Huang et al.
Jones Jeff R.
Lim Chee How
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
Tan Vibol
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