Passive release avoidance technique

Details Passive release avoidance technique Passive release avoidance technique

2006-04-04

2006-04-04

Perveen, Rehana (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S260000, C710S048000, C710S306000

Reexamination Certificate

active

07024509

ABSTRACT:
A system and method avoids passive release of interrupts in a computer system. The computer system includes a plurality of processors, a plurality of input/output (I/O) devices each capable of issuing interrupts, and an I/O bridge interfacing between the I/O devices and the processors. Interrupts, such as level sensitive interrupts (LSIs), asserted by an I/O device coupled to a specific port of the I/O bridge are sent to a processor for servicing by an interrupt controller, which also sets an interrupt pending flag. Upon dispatching the respective interrupt service routine, the processor generates two ordered messages. The first ordered message is sent to the I/O device that triggered the interrupt, informing it that the interrupt has been serviced. The second ordered message directs the interrupt controller to clear the respective interrupt pending flag. Both messages are sent, in order, to the particular I/O bridge port to which the subject I/O device is coupled. After forwarding the first message to the I/O device, the bridge port forwards the second message to the interrupt controller so that the interrupt can be deasserted before the interrupt pending flag is cleared.

REFERENCES:
patent: 5568649 (1996-10-01), MacDonald et al.
patent: 5588125 (1996-12-01), Bennett
patent: 5619706 (1997-04-01), Young
patent: 5771387 (1998-06-01), Young et al.
patent: 5875341 (1999-02-01), Blank et al.
patent: 5881296 (1999-03-01), Williams et al.
patent: 5892956 (1999-04-01), Qureshi et al.
patent: 5913045 (1999-06-01), Gillespie et al.
patent: 5933613 (1999-08-01), Tanaka et al.
patent: 5956516 (1999-09-01), Pawlowski
patent: 6021456 (2000-02-01), Herdeg et al.
patent: 6065088 (2000-05-01), Bronson et al.
patent: 6085279 (2000-07-01), Suzuki
patent: 6108741 (2000-08-01), MacLaren et al.
patent: 6163829 (2000-12-01), Greim et al.
patent: 6173351 (2001-01-01), Garnett et al.
patent: 6192425 (2001-02-01), Sato
patent: 6253275 (2001-06-01), Waldron et al.
patent: 6263397 (2001-07-01), Wu et al.
patent: 6442634 (2002-08-01), Bronson et al.
patent: 6587868 (2003-07-01), Porterfield
patent: 6604161 (2003-08-01), Miller
patent: 6629179 (2003-09-01), Bashford
patent: 2001/0027502 (2001-10-01), Bronson et al.
patent: 2001/0052043 (2001-12-01), Pawlowski et al.
de Gloria, Alessandro, et al., “A Self Timed Interrupt Controller: A Case Study in Asynchronous Micro-Architecture Design”, Sep. 19-23, 1994, IEEE Seventh Annual International ASIC Conference and Exhibit, p. 296-299.
Halang, Wolfgang A., et al., “A High-Precision Timing and Interrupt Controller to Support Distributed Real-Time Operating Systems,” Aug. 13-16, 1995, Proceedings of the 38th Midwest Symposium on Circuits and Systems, vol. 1, p. 9-12.
“PCI Local Bus Specification—Production Version,” Jun. 1, 1995, Revision 2.1, p. 257-268.
Interfacing the PC, Quality Information in one Place . . . , http://www.beyondlogic.org/interrupts/interrupt.htm, pp. 1-18.
An Introduction to Interrupts, http://goforit.unk.edu/asm/ints—1.htm, (co) 1988-2000, pp. 1-14.

Affiliated with

Also associated with

Rating

Passive release avoidance technique does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Passive release avoidance technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Passive release avoidance technique will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3541819