Passive element memory array incorporating reversible...

Details Passive element memory array incorporating reversible... Passive element memory array incorporating reversible...

2006-07-31

2009-06-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Resistive

C365S189040, C365S230060

Reexamination Certificate

active

07554832

ABSTRACT:
Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

REFERENCES:
patent: 4247918 (1981-01-01), Iwahashi et al.
patent: 5537362 (1996-07-01), Gill et al.
patent: 5673224 (1997-09-01), Chevallier et al.
patent: 5818764 (1998-10-01), Yiu et al.
patent: 5886923 (1999-03-01), Hung
patent: 5978277 (1999-11-01), Hsu et al.
patent: 6026028 (2000-02-01), Lin et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6049486 (2000-04-01), Lee et al.
patent: 6122200 (2000-09-01), Campardo et al.
patent: 6134150 (2000-10-01), Hsu et al.
patent: 6356482 (2002-03-01), Derhacobian et al.
patent: 6420215 (2002-07-01), Knall et al.
patent: 6438041 (2002-08-01), Yamada et al.
patent: 6477088 (2002-11-01), Ogura et al.
patent: 6490218 (2002-12-01), Vyvoda et al.
patent: 6525953 (2003-02-01), Johnson
patent: 6614693 (2003-09-01), Lee et al.
patent: 6618295 (2003-09-01), Scheuerlein
patent: 6704235 (2004-03-01), Knall et al.
patent: 6778437 (2004-08-01), Achter et al.
patent: 6804148 (2004-10-01), Bedarida et al.
patent: 6807103 (2004-10-01), Cavaleri et al.
patent: 6856572 (2005-02-01), Scheuerlein et al.
patent: 6859410 (2005-02-01), Scheuerlein et al.
patent: 6862223 (2005-03-01), Lee et al.
patent: 6879505 (2005-04-01), Scheuerlein
patent: 6952030 (2005-10-01), Herner et al.
patent: 6952043 (2005-10-01), Vyvoda et al.
patent: 7046577 (2006-05-01), Leconte et al.
patent: 7054219 (2006-05-01), Petti et al.
patent: 7142471 (2006-11-01), Fasoli et al.
patent: 7272052 (2007-09-01), Scheuerlein et al.
patent: 7283403 (2007-10-01), Johnson
patent: 7283420 (2007-10-01), Kim
patent: 2002/0048192 (2002-04-01), Wang et al.
patent: 2003/0002340 (2003-01-01), Lee
patent: 2003/0230733 (2003-12-01), Tanaka
patent: 2005/0052915 (2005-03-01), Herner et al.
patent: 2005/0158950 (2005-07-01), Scheuerlein et al.
patent: 2006/0002187 (2006-01-01), Forbes
patent: 2006/0145193 (2006-07-01), So et al.
patent: 2006/0146639 (2006-07-01), Fasoli et al.
patent: 2006/0250836 (2006-11-01), Herner et al.
patent: 2006/0250837 (2006-11-01), Herner et al.
patent: 2007/0069276 (2007-03-01), Scheuerlein et al.
patent: 2007/0070690 (2007-03-01), Scheuerlein et al.
patent: 2007/0072360 (2007-03-01), Kumar et al.
patent: 2007/0090425 (2007-04-01), Kumar et al.
U.S. Appl. No. 11/461,339, filed Jul. 31, 2006, entitled “Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders” by Luca G. Fasoli, Christopher J. Petti, and Roy E. Scheuerlein.
U.S. Appl. No. 11/461,364, filed Jul. 31, 2006, entitled “Method for Using a Passive Element Memory Array Incorporating Reversible Polarity World Line and Bit Line Decoders” by Luca G. Fasoli, Christopher J. Petti, and Roy E. Scheuerlein.
U.S. Appl. No. 11/461,352, filed Jul. 31, 2006, entitled “Dual Data-Dependent Busses for Coupling Read/Write Circuits to a Memory Array” by Roy E. Scheuerlein and Luca G. Fasoli.
U.S. Appl. No. 11/461,369, filed Jul. 31, 2006, entitled “Method for Using Dual Data-Dependent Busses for Coupling Read/Write Circuits to a Memory Array” by Roy E. Scheuerlein and Luca G. Fasoli.
U.S. Appl. No. 11/461,359, filed Jul. 31, 2006, entitled “Memory Array Incorporating Two Data Busses for Memory Array Block Selection” by Roy E. Scheuerlein, Luca G. Fasoli, and Christopher J. Petti.
U.S. Appl. No. 11/461,372, filed Jul. 31, 2006, entitled “Method for Using Two Data Busses for Memory Array Block Selection” by Roy E. Scheuerlein, Luca G. Fasoli, and Christopher J. Petti.
U.S. Appl. No. 11/461,362, filed Jul. 31, 2006, entitled “Hierarchical Bit Line Bias Bus for Block Selectable Memory Array” by Roy E. Scheuerlein and Luca G. Fasoli.
U.S. Appl. No. 11/461,376, filed Jul. 31, 2006, entitled “Method for Using a Hierarchical Bit Line Bias Bus for Block Selectable Memory Array” by Roy E. Scheuerlein and Luca G. Fasoli.
U.S. Appl. No. 11/496,874, filed Jul. 31, 2006, entitled “Mixed-Use Memory Array” by Roy Scheuerlein.
U.S. Appl. No. 11/496,983, filed Jul. 31, 2006, entitled “Method for Using a Mixed-Use Memory Array” by Roy Scheuerlein.
U.S. Appl. No. 11/496,870, filed Jul. 31, 2006, entitled “Mixed-Use Memory Array With Different Data States” by Roy Scheuerlein and Christopher Petti.
U.S. Appl. No. 11/497,021, filed Jul. 31, 2006, entitled “Method for Using a Mixed-Use Memory Array With Different Data States” by Roy Scheuerlein and Christopher Petti.
U.S. Appl. No. 11/461,393, filed Jul. 31, 2006, entitled “Controlled Pulse Operations in Non-Volatile Memory” by Roy Scheuerlein.
U.S. Appl. No. 11/461,399, filed Jul. 31, 2006, entitled “Systems for Controlled Pulse Operations in Non-Volatile Memory” by Roy Scheuerlein.
U.S. Appl. No. 11/461,410, filed Jul. 31, 2006, entitled “High Bandwidth One-Time Field-Programmable Memory” by Roy Scheuerlein and Christopher J. Petti.
U.S. Appl. No. 11/461,419, filed Jul. 31, 2006, entitled “Systems for High Bandwidth One-Time Field-Programmable Memory” by Roy Scheuerlein and Christopher J. Petti.
U.S. Appl. No. 11/461,424, filed Jul. 31, 2006, entitled “Reverse Bias Trim Operations in Non-Volatile Memory” by Roy Scheuerlein and Tanmay Kumar.
U.S. Appl. No. 11/461,431, filed Jul. 31, 2006, entitled “Systems for Reverse Bias Trim Operations in Non-Volatile Memory” by Roy Scheuerlein and Tanmay Kumar.
U.S. Appl. No. 11/461,343, filed Jul. 31, 2006, entitled “Apparatus for Reading a Multi-Level Passive Element Memory Cell Array” by Roy E. Scheuerlein, Tyler Thorp, and Luca G. Fasoli.
U.S. Appl. No. 11/461,367, filed Jul. 31, 2006, entitled “Method for Reading a Multi-Level Passive Element Memory Cell Array” by Roy E. Scheuerlein, Tyler Thorp, and Luca G. Fasoli.
Non-Final Office Action mailed Jan. 9, 2008, for U.S. Appl. No. 11/461,364, 19 pages.

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