Passivation of semiconductor structures having strained layers

Details Passivation of semiconductor structures having strained layers Passivation of semiconductor structures having strained layers

2008-12-22

2010-06-15

Lebentritt, Michael S (Department: 2829)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S060000, C438S062000, C438S458000, C438S795000, C257SE33001, C257SE33034

Reexamination Certificate

active

07736935

ABSTRACT:
The present invention provides, in part, methods producing multilayer semiconductor structures having one or more at least partially relaxed strained layers, where the strained layer is at least partially relaxed by annealing. In particular, the invention forms diffusion barriers that prevent diffusion of contaminants during annealing. The invention also includes embodiments where the at least partially relaxed strained layer is patterned into islands by etching trenches and the like. The invention also provides semiconductor structures resulting from these methods, and further, provides such structures where the semiconductor materials are suitable for application to LED devices, laser devices, photovoltaic devices, and other optoelectronic devices.

REFERENCES:
patent: 4994867 (1991-02-01), Biegelsen
patent: 5391257 (1995-02-01), Sullivan et al.
patent: 6214733 (2001-04-01), Sickmiller
patent: 6794276 (2004-09-01), Letertre et al.
patent: 7018909 (2006-03-01), Ghyselen et al.
patent: 7273798 (2007-09-01), Lester et al.
patent: 7282381 (2007-10-01), Feltin et al.
patent: 2003/0064535 (2003-04-01), Kub et al.
patent: 2004/0192067 (2004-09-01), Ghyselen et al.
patent: 2004/0253792 (2004-12-01), Cohen et al.
patent: 2005/0250294 (2005-11-01), Ghyselen et al.
patent: 2006/0128117 (2006-06-01), Ghyselen et al.
patent: 2006/0175608 (2006-08-01), Celler
patent: 2006/0205180 (2006-09-01), Henley et al.
patent: 2006/0211219 (2006-09-01), Henley et al.
patent: 2007/0048975 (2007-03-01), Chen et al.
patent: 2007/0069225 (2007-03-01), Krames et al.
patent: 2007/0072324 (2007-03-01), Krames et al.
patent: 2007/0241353 (2007-10-01), Taki
patent: 2007/0278622 (2007-12-01), Lester et al.
patent: 2007/0298549 (2007-12-01), Jurczak et al.
patent: 2008/0113496 (2008-05-01), Keller et al.
patent: 2008/0169483 (2008-07-01), Kasai et al.
patent: 2009/0050917 (2009-02-01), Nakagawa et al.
patent: 0651439 (1995-05-01), None
patent: 0 858 110 (1998-08-01), None
patent: 1 671 361 (2007-04-01), None
patent: 1901345 (2008-03-01), None
patent: 2775121 (1999-08-01), None
patent: 2895420 (2007-06-01), None
patent: 2895562 (2007-06-01), None
Hobart, K.D. et al., “Compliant Substrates: A Comparative Study of the Relaxation Mechanisms of Strained Films Bonded to High and Low Viscosity Oxides”, Journal of Electronic Materials, vol. 29, No. 7, pp. 897-900 (2000).
L. Di Cioccio et al., “III—V Layer Transfer Onto Silicon and Applications”, Phys. Stat. Sol., vol. (a) 202, No. 4, pp. 509-515 (2005).
M. Kostrzewa et al, “Feasibility of Strain Relaxed InAsP and InGaAs Compliant Substrates”, pp. 437-440 (2003).
P. M. Mooney et al., “Elastic Strain Relaxation in Free-Standing SiGe/Si Structures”, Applied Physics Letters, vol. 84, No. 7, pp. 1093-1095 (2004).
Haizhou Yin et al., “Buckling Suppression Of SiGe Islands On Compliant Substrates”, Journal of Applied Physics, vol. 94, No. 10, pp. 6875-6882 (2003).
Haizhou Yin et al., “Strain Relaxation Of SiGe Islands On Compliant Oxide”, Journal of Applied Physics, vol. 91, No. 12, pp. 9716-9722 (2002).
Haizhou Yin et al., “Tunable Uniaxial Vs Biaxial In-Plane Strain Using Compliant Substrates”, Applied Physics Letters, vol. 87, pp. 061922-1-061922-3 (2005).
R. Huang et al., XP009112211, “Mechanics Of Relaxing SiGe Islands On A Viscous Glass,” Acta Mechanica Sinica (English Series), vol. 18, No. 5, pp. 441-456 (2002).
European Search Report for EP08290757.7 dated Mar. 16, 2009.
Haizhou Yin et al., “Fully-depleted Strained-Si on Insulator NMOSFETs without Relaxed SiGe Buffers”, IEDM International Electron Devices Meeting, pp. 03-53-03-56 (2003).
C. X. Peng et al., “Influence of GaN polarity and intermediate-temperature buffer layers on strain relaxation and defects”, PHYSICA Bvol.391, No. 1, pp. 6-11 (2007).
European Search Report for EP 08 29 0759 dated Apr. 14, 2009.

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