Passivation of power semiconductor device

Details Passivation of power semiconductor device Passivation of power semiconductor device

2007-11-13

2007-11-13

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000, C257S401000, C257S578000

Reexamination Certificate

active

11095921

ABSTRACT:
A vertical power semiconductor device comprises a substrate including a first layer that is a first conductivity type. A first conductive region is provided proximate an upper surface of the substrate, the first conductive region being a second conductivity type that is different from the first conductivity type. A first electrode is provided proximate the upper surface of the substrate and coupled to the first conductive region. A second electrode is provided proximate a lower surface of the substrate. A passivation structure including first and second dielectric layers provided over the upper surface of the substrate. One or more field plates of first type are provided between the first and second dielectric layers.

REFERENCES:
patent: 2004/0009638 (2004-01-01), Tanaka
patent: 2004/0084753 (2004-05-01), Fruth et al.
patent: 2006/0049406 (2006-03-01), Amaratunga et al.

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