Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-01-31
2009-12-01
Garber, Charles D. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S426000, C438S427000, C438S428000, C438S435000, C257SE21546, C257SE21547, C257SE21548, C257SE21549, C257SE21550
Reexamination Certificate
active
07625805
ABSTRACT:
Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar surface formed by the isolating layers. The filling is planarized and a portion of the filling located in the trench interior is removed. A portion of the isolation layers are then removed and a portion of the filling is removed so that the filler and the isolation layers in the trenches are at about the same level. A covering layer is then deposited. The covering layer extends above the surface of the wafer and into the trenches down to the filler and the isolation layers. The covering layer is additionally planarized to about the top of the trenches.
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Eckoldt Uwe
Lerner Ralf
Ahmadi Mohsen
Garber Charles D.
Stevens & Showalter LLP
X-FAB Semiconductor Foundries AG
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