Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-29
2001-01-30
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S600000, C438S132000, C438S006000, C257S529000
Reexamination Certificate
active
06180503
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for manufacturing memory arrays with fusible links.
(2) Description of Prior Art
Computer memory chips consist of vast arrays of storage cells which can be addressed by wordlines and bitlines. Each cell corresponds to one bit. The most commonly used cell design used in current dynamic random access memories(DRAMs) comprise a transfer gate(usually an MOS field-effect-transistor(MOSFET) and a storage node consisting of a capacitor. DRAM cells are, by necessity of high density and of simple design. To this end, the MOSFET-capacitor combination serves quite well. Static-random-access-memories(SRAMs) are slightly more complex, requiring four to six MOSFETs per cell.
The cell quantity requirements for memory are increasing at a phenomenal rate. Whereas the SRAMs of 1991 were of the order of 4 megabits, the density by the year 2001 is predicted to be 256 megabits or more. DRAMs have even greater cell density requirements. See e.g. S. Wolf, “Silicon Processing for the VLSI Era”, Vol. II, Lattice Press, Sunset Beach, Calif. (1990) p.598ff, and Vol. III (1995) p.275. The occurrence of a single defect in such a complex integrated circuit(IC) renders the entire body useless.
Obviously, the manufacturing functional yield of memory chips would rapidly approach zero if steps were not taken to circumvent such defective components. To this end, additional segments of memory circuits are provided on the IC chip as replacements for defective segments. Fortunately, memory arrays, by virtue of their repetitive design, lend themselves particularly well to the incorporation of such redundant segments. Although, additional space is required for these extra circuits, the yield benefits they provide make them very cost effective.
The manner in which these redundant segments are utilized and defective segments deleted is accomplished by means of laser trimming. A description of the design layout and implementation of such redundant circuits need not be given here but may be found in Motonami et.al., U.S. Pat. No. 5,241,212. The segments are provided with fusible links or fuses which are ruptured or blown as required, by a laser, after IC processing has been completed and functional testing with probes is possible. The functional testing determines which segments are defective and a laser, usually a neodymium YAG laser, is directed at the appropriate fusible links, thereby breaking the circuit.
The fusible links are formed as part of one of the metallization layers of the IC. Typically, a lower level, such as a polysilicon level is used. This level would, for example, contain the word-lines of a DRAM array. Prior to Laser trimming, the interlevel dielectric layers above the fusible link are sometimes removed entirely and replaced by a thinner protective layer to provide a short uniform path for the laser and confine the resultant debris. In other cases, the thick dielectric layers are etched down to a pre-determined thickness above the link. The laser energy required to blow the fuse is proportional to the thickness of the dielectric material above the fuse.
The laser access window is commonly opened in a final etch step after the uppermost metallization level has been patterned and a final passivation layer has been deposited. The passivation layer is patterned to form access openings to bonding pads in the uppermost metallization level and, simultaneously form access openings to the fuses. At the bonding pads, the etch must penetrate the passivation layer, which is between about 0.5 and 1.5 microns thick, and a 200 to 400 Angstrom thick ARC (anti-reflective coating) on the pad. However, the fuse openings must pass through, not only the passivation layer, but an additional thickness of subjacent insulative layers varying between about 0.8 and 1.4 microns. Even though etch rate selectivities favorable for etching insulative material over metallization are used, it is difficult to etch the entire fuse opening simultaneously with the bonding pad openings without either degrading the bonding pad by over etching, or leaving too much or too little or no insulator over the fuses. In current technology, the ARC over the bonding pads must also be removed by the passivation layer patterning step. This requires significant over-etching of the bonding pad and often results in excessive or total removal of insulative layer over the fuses. Exposure of the fuses subjects them to atmospheric moisture and corrosion.
Rodriguez, et.al., U.S. Pat. No. 5,821,160 addresses the problem of cumulative non-uniformities in an SRAM (static random access memory) developed in the multiple insulative layers between the fuses an the passivation layer by providing an etch stop in a polysilicon layer which lies just one insulative layer above the fuses. The polysilicon layer which used to form the poly load resistors of the SRAMs is patterned to include plates of polysilicon over the fuse regions. These plates are located on a layer of about 4,000 Angstroms of silicon oxide which is formed directly on the fuses. The plates serve as an etch stop during the fuse opening etch so that a uniform oxide layer remains over the fuses. Although this procedure assures a uniform thickness of insulator over the fuses, a large etch depth differential between the bonding pad openings and the fuse access openings still remains.
Lippitt, U.S. Pat. No. 5,235,205, like Rodriguez provides an etch stop, patterned in a metallization level over a fuse, to permit the opening both bonding pads completely and fuse access openings to a fixed level without using a time dependent etch. However, in both instances, unless the etch stop material can be subsequently etched selectively while the bonding pads are exposed, the etch stop cannot be removed without using an additional photomask to protect the bonding pads. This requirement, in order to save a photolithographic step is not a welcome design limitation.
Fukuhara, et.al., U.S. Pat. No. 5,618,750 shows methods for forming fuse structures which have non-corrosive elements to prevent corrosion damage to surrounding components after the fuse is blown. Lee, et.al., U.S. Pat. No. 5,567,643 describes a guard ring structure around a fuse which protects nearby components from corrosion damage after the fuse is blown. Sanchez, et.al., U.S. Pat. No. 5,789,795 shows the shows the formation of an anti-fuse wherein a dielectric etch stop layer is deposited directly on the layer of anti-fuse material.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a method for progressively forming fuse access openings and simultaneously etching a passivation layer and bonding pad openings.
It is another object of this invention to provide a method for retarding fuse access opening formation during via formation by the use of transient etch stop layers.
It is another object of this invention to provide a method for improving the uniformity of insulative layers over fuse links while at the same time sufficiently over-etching vias and passivation layer access openings to thoroughly remove ARC layers.
It is yet another object of this invention to provide a method for patterning a passivation layer to form access to bonding pads and laser access openings with a single photolithographic mask.
These objects are accomplished by using etching the laser access opening in two steps using a transient etch stop layer between the first and second step. After a fuse is formed in a polysilicon level, an etch stop pad is patterned in a higher level metal or polysilicon level over the rupture zone of the fuse. The fuse access opening is then partially formed concurrent with a via etch which penetrates a relatively thick IMD layer. The etch stop pad limits the penetration over the rupture zone to only the IMD layer. The etch stop pad is removed during a metal patterning etch. The second and final portion of the access opening is then formed during patterning of the passi
Lin Hsing-Lien
Tzeng Wen-Tsing
Yang Chun-Pin
Ackerman Stephen B.
Booth Richard
Kennedy Jennifer M.
Saile George O.
Vanguard International Semiconductor Corporation
LandOfFree
Passivation layer etching process for memory arrays with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Passivation layer etching process for memory arrays with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Passivation layer etching process for memory arrays with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2528089