Passivation integrity improvements

Details Passivation integrity improvements Passivation integrity improvements

1999-09-02

2002-03-19

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

C438S761000, C438S791000, C257S635000

Reexamination Certificate

active

06358862

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor fabrication processing and more particularly to a method for improving passivation integrity for semiconductor devices, such as random access memories.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, after patterning the final metal layer, such as aluminum (Al), into metal lines, a passivation layer is deposited over the entire top surface of the semiconductor assembly. The passivation layer is an insulating, protective layer that prevents mechanical and chemical damage during assembly and packaging of individual semiconductor devices. The passivation layer must possess gettering or barrier properties that enable the film to prevent sodium ions and other fast-diffusing metallic contaminants from reaching the underlying metal lines. In general, the thicker the passivation layer the better, since a thicker layer will provide better protection. However, because the thicker chemical vapor deposited (CVD) films, especially silicon nitride films, have high stress and a higher tendency to crack, there is normally an upper limit to the thickness.
Silicon nitride has been used as passivation material because it provides an impermeable barrier to moisture and mobile ion impurities (e.g., sodium) and also forms a durable coat that protects the device against scratching. However, because the passivation layer must be deposited over metal films, only plasma enhanced chemical vapor deposited (PECVD) nitride films may be used for this application since a PECVD nitride film is deposited at approximately 400° C. (a low deposition temperature that is less than the melting point of the underlying metal, typically no greater than 450° C., must be used in order to avoid reflowing and thus thinning of the metal). Unfortunately, PECVD nitride films normally exhibit a high mechanical stress, which can cause cracks in the film during subsequent heating steps.
FIG. 1
depicts a conventional fabrication process used to form typical passivation layers for a semiconductor device. In
FIG. 1
, a first tetra-ethyl-ortho-silicate (TEOS) layer
12
has been formed over metal lines
11
and then facet etched. A second TEOS layer
13
is formed on first TEOS layer
12
. As shown, TEOS layer
13
pinches off the gap between metal lines
11
. Then, a nitride passivation layer
14
is deposited onto TEOS layer
13
. Because nitride layer
14
conforms to the contour of TEO S layer
13
, stress point
15
forms directly above the pinch off line. Stress caused by such forces as subsequent heating can cause a fracture or crack in nitride layer
14
due to stress point
15
. Obviously, any crack in nitride layer
14
will render the passivation qualities less than optimal, as a crack will allow the penetration of mobile ions and moisture into the underlying structures of the semiconductor device.
The present invention discloses a method to reduce cracking of passivation films by reducing stress and thus improving the barrier capability of the passivation film to mobiles ion impurities and moisture.
SUMMARY OF THE INVENTION
An exemplary implementation of the present invention comprises passivation protection for semiconductor assemblies and a method to form them. The general concept of the present invention is to provide passivation protection using partially conformal passivation layers so that the resulting structure will be resistant to stress caused by expansion and contraction of neighboring structures or layers of material in order to avoid cracking while providing passivation protection that is an excellent mobile ion barrier to ionized alkali metal atoms, such as sodium (Na
+
), potassium (K
+
), and lithium (Li
+
).
In an exemplary implementation, passivation protection is formed by placing a layer of oxide over patterned metal lines having sidewalls. Next, a first passivation layer of silicon nitride is formed on the layer of oxide such that the first passivation layer of silicon nitride resides along the sidewalls of metal lines and preferably, pinches itself off to form a gap between the metal lines. This method develops a passivation structure wherein the passivation layer of silicon nitride is resistant to stress caused by the expansion and contraction of neighboring structures or layers of material. Next, a facet etch is performed to remove material from the edges of the first passivation layer of silicon nitride. Finally, a second passivation layer of silicon nitride is formed on the first passivation layer of silicon nitride, wherein the contour of the second passivation layer of silicon nitride is such that the second passivation layer of silicon nitride is resistance to stress caused by the expansion and contraction of neighboring structures or layers of material.


REFERENCES:
patent: 5372969 (1994-12-01), Moslehi
patent: 5644153 (1997-07-01), Keller
patent: 5880018 (1999-03-01), Boeck et al.
patent: 5880026 (1999-03-01), Xing et al.
patent: 5903041 (1999-03-01), La Fleur et al.
patent: 5985767 (1999-11-01), Roberts et al.
patent: 6037249 (2000-03-01), Chiang et al.
patent: 6051509 (2000-04-01), Tsuchiaku
patent: 6107183 (2000-08-01), Sandhu et al.
patent: 6141365 (2000-10-01), Bowler
patent: 6150190 (2000-11-01), Stankus et al.
patent: 6160316 (2000-12-01), Gardner et al.
patent: 6208015 (2001-03-01), Bandyopadhyay et al.

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