Passivation film on a semiconductor wafer

Details Passivation film on a semiconductor wafer Passivation film on a semiconductor wafer

2000-02-28

2003-02-18

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S256000, C257S306000, C257S368000, C438S622000, C438S624000, C438S626000, C438S633000, C438S692000, C438S697000, C438S762000, C438S780000

Reexamination Certificate

active

06521922

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a passivation film, and more particularly, to a passivation film on a semiconductor wafer.
2. Description of the Prior Art
In semiconductor processing, the frames of the ICs are formed on the semiconductor wafer after completing the primary processes, like metallization and planarization. These ICs are easily damaged by inadvertent collisions or long-term exposure to humidity and moisture. Therefore, a passivation film is formed on the surface of the semiconductor wafer to protect the underlying ICs.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional schematic diagram of a passivation film
24
formed on a semiconductor wafer according to the prior art. The passivation film
24
is used to protect an erasable programmable read-only memory (EPROM), or flash memory, that is formed on the semiconductor wafer
10
. The semiconductor wafer
10
comprises a dielectric layer
12
and a patterned conductive layer
14
positioned on the dielectric layer
12
. The surface of the semiconductor wafer
10
is covered by the passivation film
24
. The passivation film
24
comprises an ultra-violet silicon nitride (UVSiN) layer
16
positioned on the dielectric layer
12
and the conductive layer
14
, a spin-on glass (SOG) layer
18
positioned on the UVSiN layer
16
, a silicon-oxy-nitride layer (SiON) layer
20
positioned on the SOG layer
18
, and a phosphosilicate glass (PSG) layer
22
positioned on the SiON layer
20
.
According to a prior art method of forming the passivation film
24
, a chemical vapor deposition (CVD) process is first performed to deposit the UVSiN layer
16
of uniform thickness on the semiconductor wafer
10
to cover the surface of the dielectric layer
12
and the conductive layer
14
. Then, SOG is coated on the semiconductor wafer to fill the spaces inside the conductive layer
14
. A heat treatment is used to cure the SOG so as to form the SOG layer
18
on the UVSiN layer
16
. Finally, the SiON layer
20
and the PSG layer
22
are sequentially deposited on the semiconductor wafer
10
. This completes the passivation film
24
.
However, SOG possesses a gap filling ability that is only applicable to a line width that is wider than a 0.5-micrometer semiconductor process. As for narrower semiconductor processes, SOG cannot fill the concavities formed inside the conductive layer
14
, and thus will bring about voids. This will decrease the cracking-resistance, water-resistance, and ion-resistance of the passivation film
24
. Hence, the passivation film
24
fails to adequately protect the underlying ICs.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a passivation film on a semiconductor wafer to fill the concavities on the semiconductor wafer so as to prevent voids and thus ensure the ability of the passivation layer to protect the underlying ICs.
In a preferred embodiment, the present invention provides a passivation film on a semiconductor wafer. The semiconductor wafer comprises a dielectric layer and a patterned conductive layer on the dielectric layer. The passivation film comprises a high density plasma (HDP) oxide layer positioned on the surface of the conductive layer and on the surface of the dielectric layer that is not covered by the conductive layer, a silicon nitride layer positioned on the HDP oxide layer, and a water-resistant layer positioned on the silicon nitride layer. The HDP oxide layer possesses good gap filling abilities to fill the spaces inside the conductive layer.
It is an advantage of the present invention that the passivation film comprises the HDP oxide layer, which can completely fill the spaces inside the conductive layer to prevent voids and so protect the underlying ICs.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5858870 (1999-01-01), Zheng et al.

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