Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-07-12
2003-12-23
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S761000, C438S787000
Reexamination Certificate
active
06667230
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a process of making a flip chip, and more particularly to a process involving a unique passivation and planarization process for making a flip chip.
BACKGROUND OF THE INVENTION
A flip chip microelectronic assembly includes a direct electrical connection of a face down (that is, “flipped”) electronic components onto substrates, such as ceramic substrates, circuit boards, or carriers using conductive bump bond pads of the chip. Flip chip technology is quickly replacing older wire bonding technology that uses face up chips with the wire connected to each pad on the chip.
The flip chip components used in flip chip microelectronic assemblies are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and MEM devices are also being used in flip chip form. Flip chips are also known as “direct chip attach” because the chip is directly attached to the substrate, board, or carrier by the conductive bumps.
The use of flip chip packaging has dramatically grown as a result of the flip chips advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the widening availability of flip chip materials, equipment and services. In some cases, the elimination of old technology packages and bond wires may reduce the substrate or board area needed to secure the device by up to 25 percent, and may require far less height. Further, the weight of the flip chips can be less than 5 percent of the old technology packaging devices.
Flip chips are advantageous because of their high-speed electrical performance when compared to other assembly methods. Eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path resulting in a high speed off-chip interconnection.
Flip chips also provide the greatest input/output connection flexibility. Wire bond connections are generally limited to the perimeter of the chip or die, driving the die sizes up as a number of connections have increased over the years. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Further, flip chips can be stacked in three-D geometries over other flip chips or other components.
Flip chips also provide the most rugged mechanical interconnection. Flip chips when underfilled with an adhesive such as an epoxy, can withstand the most rugged durability testing. In addition to providing the most rugged mechanical interconnection, flip chips can be the low cost interconnection for high-volume automated production.
The bumps on the flip chip assembly serve several functions. The bumps provide an electrical connective path from the chip (or die) to the substrate on which the chip is mounted. A thermally conductive path is also provided by the bumps to carry heat from the chip to the substrate. The bumps also provide part of mechanical mounting of the chip to the substrate. A spacer is provided by the bumps that prevents electrical contact between the chip and the substrate connectors. Finally, the bump acts as a short lead to relieve mechanical strain between the chip and the substrate.
Despite all of these advantages, these microelectronic assemblies are very delicate structures, the design of which and the manufacturing of create difficult and unique technical problems. Continuous efforts by those working in the art are being undertaken to improve the performance, reliability and useful life of microelectronic assemblies, particularly those using flip chips. More particularly, many problems needed to be solved, and improvements made in the process steps of making flip chips.
Some of the difficulties associated with accurately and reliably placing solder bumps on a wafer stem from the wafer fabrication processes. Wafer fabrication involves film deposition and growth processes, followed by repeated patterning to form device and interconnection structures. Advance integrated circuits require multiple levels of metallization, sometimes eight or more layers with each metal layer separated by in interlayer dielectric. As a result of multilevel interconnect wiring and device structures at different locations within the wafer, a number of different steps are created in the different layers. Wafer topography describes the nonplanar surface of the wafer layers, produced during the wafer manufacturing processes. Wafer topography becomes more pronounced with each additional layer. Acceptable step coverage and gap-fill are critical for chip yield and long-term reliability.
Higher chip packing density demands have resulted in increased topography of wafers. The desire for multilevel metal technology in integrated chip design is compounded by the ever present need to decrease the device size and interconnection dimensions. Surface topography in many advanced integrated circuits have deep steps and higher aspect ratios for gaps, making step coverage and gap fill much more difficult. A major negative consequence of topography is a loss of line width control during photolithography. Photoresist thickness variations due to topography inhibit submicron photolithography. It is also much more difficult to pattern nonuniform photoresist thickness over etched steps. Some of these factors greatly impact the ability to effectively and reliably place bumps on a wafer.
Planarization is one method of addressing or overcoming the negative impact of topography created in the multilevel wafer fabrication process. A planarized wafer has a flat surface with minimal layer thickness variation, that is, minimal topography on each layer. Filling in low features or removing high features are two ways to planarize a wafer surface. Planarizing the wafer surface is critical for follow-on process steps such as lithography and can actually serve to increase device yield by removing undesirable foreign material on the wafer surface during the actual planarization process.
In general, there are four different types of wafer planarization. In smoothing planarization, step height corners are rounded and side walls sloped, but the height is not significantly reduced. In partial planarization, the step corners are also rounded and side walls sloped, plus a local reduction in step height is achieved. In local planarization, small gaps (1-10 micrometers) are completely filled on local areas within the die, but the total step height across the wafer is not significantly reduced. In global planarization, local planarization is achieved plus significant reduction in the total step height across entire wafer surface is accomplished. This is also referred to as uniformity.
There have been three traditional methods of wafer planarization including: etchback, glass reflow, and spin on films. A topography created by surface features can be smoothed by applying a thick layer of a dielectric or other material followed by the application of the sacrificial layer of planarization material, such as a photoresist or spin on glass. The sacrificial material fills voids and low spots on the surface. Etching of the sacrificial layer is usually done by a dry etch to smooth the surface features and remove high features at a faster rate than lower features. This processes known as etchback planarization. The etching is continued until the dielectric reaches a final thickness, with the planarizing material still filling the low areas. There are different variations of etchback planarization depending on the features and metal layers used. Etchback planarization is a local planarization of topography that smooths the surface over closely spaced steps. However, etchback does not provide global planarization.
Borophosphosilicate glass (BPGS) and other doped oxides have been used for interlayer dielectric applications, and are often deposited with atmospheric pressure chemical vapor deposition. Glass reflow is the heating of a doped oxide to cause the material to flow at elevated temperatures. For example, borophosphosilicate glass annealed in a high temperat
Chen Dian-Hau
Lin Kwang-Ming
Wu Lin-June
Cuneo Kamand
Geyer Scott B.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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