Passivated deep p/n junction

Details Passivated deep p/n junction Passivated deep p/n junction

1986-02-18

1987-06-30

Weisstuch, Aaron

Metal treatment

Barrier layer stock material, p-n type

With non-semiconductive coating thereon

136255, 136261, 148 15, 148176, 357 30, 357 91, H01L 2912, H01L 3106

Patent

active

046768459

ABSTRACT:
A passivated deep p
junction obtained by ion implantation is disclosed. The passivated deep p
junction is formed in a wafer, preferably a silicon wafer, thus providing an emitter region that is both lightly doped and extending to a depth of about one micrometer. The emitter region in turn is provided with a surface layer so as to reduce surface recombination. Preferably, the surface layer is a silicon oxide layer of about 0.01 micrometer thickness. The p
junction is obtained by ion implantation whereby the dopant is introduced at room temperature and then distributed thermally. The surface layer preferably is formed near the end of the thermal distribution by admitting a small amount of dry oxygen to a gas stream, and passing the gas stream along the surface of the wafer.

REFERENCES:
J. A. Minnucci et al, IEEE Transactions on Electron Devices, vol. ED-27, pp. 802-806 (1980).
A. Usami et al, Conf. Record, 17th IEEE Photovoltaic Specialists Conf. (1984), pp. 547-552.
C. T. Ho et al, Solar Cells, vol. 11, pp. 29-39 (1984).
M. P. Godlewski et al, Conf. Record, 14th IEEE Photovoltaic Specialists Conf., (1980), pp. 166-171.
R. A. Arndt et al, Conf. Record, 15th IEEE Photovoltaic Specialists Conf. (1981), pp. 92-96.
V. E. Lowe et al, IEEE Transactions on Electron Devices, vol. ED-31 (No. 5), May 1984, pp. 626-629.

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