Passing a received packet for modifying pipelining...

Electrical computers and digital processing systems: processing – Processing control – Processing sequence control

Reexamination Certificate

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Details

C712S025000, C712S030000, C712S201000

Reexamination Certificate

active

07000098

ABSTRACT:
In one embodiment, a method is provided. The method of this embodiment includes generating, by a processor that includes a plurality of processing engines capable of executing program instructions, a packet. The method of this embodiment also includes transmitting the packet to at least one of the processing engines. Additionally, the method of this embodiment also includes, in response, at least in part to receipt of the packet by the at least one of the processing engines, modifying at least in part, by the at least one of the processing engines, a set of program instructions that the at least one processing engine is capable of executing. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

REFERENCES:
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patent: 6172990 (2001-01-01), Deb et al.
patent: 2003/0158759 (2003-08-01), Kannenberg
Intel Network Infrastructure Processors, Extending Intelligence in the Network, Intel in Communications, Intel Literatute Center, 16 pages.
Intel XScale Microarchitecture, Technical Summary 14 pages.
Intel XScale Core, Developers Manual, Dec. 2000, 220 pages.
Tennenhouse et al, “A Survey of Active Network Research” IEEE Communications Magazine vol. 35, No. 1, Jan. 1997.
INTEL, IXP1200 Network Processor Family, Hardware Reference Manual, Dec. 2001, pp. 17-50.

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